Hi Richard I queue them and run the CI, I have it ready, waiting for the denx site to be up again
Michael On Mon, Jan 12, 2026 at 6:30 PM Michael Nazzareno Trimarchi <[email protected]> wrote: > > Hi > > My fault, I was thinking to already have picked them, I will do > > On Mon, Jan 12, 2026 at 6:09 PM Richard GENOUD > <[email protected]> wrote: > > > > Hi Michael, > > Le 31/10/2025 à 07:43, Michael Nazzareno Trimarchi a écrit : > > > Hi Richard > > > > > > On Tue, Oct 28, 2025 at 10:13 AM Richard Genoud > > > <[email protected]> wrote: > > >> > > >> Hi everyone, > > >> > > >> This patch series introduce H6/H616 NAND controller support (but not yet > > >> the DMA/MDMA part). > > >> > > >> All the work was done on a H616 board with a Kioxia TC58NVG1S3HTA00 NAND > > >> chip. > > >> ECC is supported, as well as scrambling. > > >> > > >> Support for booting from NAND is not part of this series, but it's almost > > >> ready. (It needs quite some modifications in sunxi-spl-image-builder.c > > >> and sunxi_toc0.c) > > >> > > >> H6 SoC has not been tested, but it shares all registers with H616, plus > > >> some registers dedicated to Embedded Crypto Engine that H616 lacks. > > >> > > >> This IP has quite some register fields modified from the A10/A23, but in > > >> the end, it works more or less the same. > > >> Main differences with A10/A23 are: > > >> - The need for 2 more clocks (for ECC and MBUS) > > >> - The use of a new USER_DATA_LEN register > > >> - More ECC strengths (44, 52, 68, 72, 76 and 80 bits / 1KB) > > >> - MDMA based on chained buffers > > >> - some registers layouts have changed (mainly due do the stronger ECC) > > >> > > >> Patches 1 and 2 are small fixes > > >> > > >> Patches 3-6 harmonize the registers definitions between U-Boot and SPL, > > >> and ultimately merge those definitions in an include file, without > > >> functional change, removing the usage of sunxi_ccm_reg on the way. > > >> > > >> Patches 7-19 are paving the way to the introduction of H6/H616 NAND > > >> controller by adding per SoC capabilities for both drivers. They are > > >> small for an easier review, without functional change. > > >> > > >> Patches 20-21 are adding missing NAND related clocks definitions for > > >> H6/H616 > > >> > > >> Patch 22 adds the support for H6/H616 NAND controller in U-Boot. > > >> > > >> Patch 23 adds the support for H6/H616 NAND controller in SPL. > > >> > > >> Patch 24 fixes warnings in sunxi_nand_spl.c > > >> > > >> A similar series for this NAND controller support in Linux has been sent > > >> and being reviewed. > > >> > > >> Changes from v1: > > >> - pick-up reviewed-by > > >> - use a readl() loop instead of memcpy_fromio() in patch 2 as suggested > > >> by Andre > > >> - remove cosmetic in patches that are beyond cosmetic changes > > >> - remove usage of struct sunxi_ccm_reg, suggested by Andre > > >> - indent @caps member description in comment > > >> - give more informations on PAT_FOUND registers in commit message > > >> - drop NFC_ECC_BLOCK_SIZE_MSK which was just a 1bit mask for the very > > >> same bit NFC_ECC_BLOCK_512 > > >> - add missing MACH_SUN50I_H6 in Kconfig > > >> > > >> Richard Genoud (24): > > >> mtd: rawnand: sunxi: cosmetic: remove needless comment > > >> mtd: rawnand: sunxi_spl: fix pointer from integer without a cast > > >> mtd: rawnand: sunxi_spl: harmonize register defines with non spl file > > >> mtd: rawnand: sunxi_spl: cosmetic: use definitions from > > >> linux/mtd/rawnand.h > > >> mtd: rawnand: sunxi: remove usage of struct sunxi_ccm_reg > > >> mtd: rawnand: sunxi: merge register definitions for > > >> sunxi_nand{,_spl}.c > > >> mtd: rawnand: sunxi: add per SoC capabilities > > >> mtd: rawnand: sunxi: move ECC_ERR_CNT register offset in SoC caps > > >> mtd: rawnand: sunxi: move USER_DATA register offset in SoC caps > > >> mtd: rawnand: sunxi: move ECC_PAT_FOUND register in SoC caps > > >> mtd: rawnand: sunxi: add has_ecc_block_512 capability > > >> mtd: rawnand: sunxi: move NFC_ECC_MODE offset in SoC caps > > >> mtd: rawnand: sunxi: introduce reg_pat_id in sunxi_nfc_caps > > >> mtd: rawnand: sunxi_spl: add per SoC capabilities > > >> mtd: rawnand: sunxi: move NFC_RANDOM_EN register offset in SoC caps > > >> mtd: rawnand: sunxi: introduce reg_spare_area in sunxi_nfc_caps > > >> mtd: rawnand: sunxi_spl: use NFC_ECC_ERR_MSK and NFC_ECC_PAT_FOUND > > >> mtd: rawnand: sunxi_spl: increase max_oobsize for 2KiB pages > > >> mtd: rawnand: sunxi_spl: use NFC_ECC_MODE and NFC_RANDOM_SEED macros > > >> sunxi: clock: H6: add NAND controller clock registers > > >> clk: sunxi: Add MBUS Master Clock Gating Register > > >> mtd: rawnand: sunxi: add support for H6/H616 nand controller > > >> mtd: rawnand: sunxi_spl: add support for H6/H616 nand controller > > >> mtd: rawnand: sunxi_spl: Fix cast to pointer from integer warnings > > >> > > >> arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 1 + > > >> .../include/asm/arch-sunxi/clock_sun50i_h6.h | 24 ++ > > >> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 1 + > > >> .../include/asm/arch-sunxi/clock_sun8i_a83t.h | 1 + > > >> arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 2 + > > >> board/sunxi/board.c | 19 +- > > >> drivers/clk/sunxi/clk_h6.c | 2 + > > >> drivers/clk/sunxi/clk_h616.c | 2 + > > >> drivers/mtd/nand/raw/Kconfig | 3 +- > > >> drivers/mtd/nand/raw/sunxi_nand.c | 308 +++++++++-------- > > >> drivers/mtd/nand/raw/sunxi_nand.h | 228 +++++++++++++ > > >> drivers/mtd/nand/raw/sunxi_nand_spl.c | 322 +++++++++++------- > > >> 12 files changed, 629 insertions(+), 284 deletions(-) > > >> create mode 100644 drivers/mtd/nand/raw/sunxi_nand.h > > >> > > > > > > I will pick the series over the weekend, check CI, and check better > > > all the patches that already > > > get reviewed anyway > > > > Any news? > > Sorry, I have picked the patches assigned to me, but now I found out > that I miss your series because > was not assigned to me. Give me a couple of days > > Michael > > > > > > > Regards, > > Richard > > > > > > > > > > MIchael > > > > > >> > > >> base-commit: 2ba64e303b2706e5c42a6bf982326d632342ca66 > > >> -- > > >> 2.47.3 > > >> > > > > > > -- > > Richard Genoud, Bootlin > > Embedded Linux and Kernel engineering > > https://bootlin.com > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > [email protected] > __________________________________ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > [email protected] > www.amarulasolutions.com -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 [email protected] __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 [email protected] www.amarulasolutions.com
