Replace underscores with hyphens in the PHY timing configuration property names to follow standard devicetree naming conventions: - phy-gate-lpbk_ctrl-delay-sd-ds -> phy-gate-lpbk-ctrl-delay-sd-ds - phy-gate-lpbk_ctrl-delay-sd-hs -> phy-gate-lpbk-ctrl-delay-sd-hs
Signed-off-by: Tanmay Kathpalia <[email protected]> --- arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi index 5a7aa5841e3..417575fa0f0 100644 --- a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi @@ -3,7 +3,7 @@ * U-Boot additions * * Copyright (C) 2024 Intel Corporation <www.intel.com> - * Copyright (C) 2025 Altera Corporation <www.altera.com> + * Copyright (C) 2025-2026 Altera Corporation <www.altera.com> */ #include "socfpga_agilex5-u-boot.dtsi" @@ -119,13 +119,13 @@ /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; - cdns,phy-gate-lpbk_ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; /* SD card high speed and UHS-I SDR25 mode timing configuration */ cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; - cdns,phy-gate-lpbk_ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>; cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; -- 2.43.7
