On Mon, Jan 26, 2026 at 09:29:36PM +0530, Balaji Selvanathan wrote: > Add SDCC (SD Card Controller) clock support for QCS615 platform to > enable eMMC functionality. This includes adding SDCC1 and SDCC2 clock > gates, implementing SDCC1 apps clock rate configuration > and adding QCS615 RPMH clock compatibility to the stub > driver to handle device tree clock controller references. > > Signed-off-by: Balaji Selvanathan <[email protected]> > --- > drivers/clk/clk-stub.c | 2 +- > drivers/clk/qcom/clock-qcom.h | 1 + > drivers/clk/qcom/clock-qcs615.c | 10 ++++++++++ > 3 files changed, 12 insertions(+), 1 deletion(-)
Reviewed-by: Sumit Garg <[email protected]> -Sumit > > diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c > index 117266ac778..1bc749e47b3 100644 > --- a/drivers/clk/clk-stub.c > +++ b/drivers/clk/clk-stub.c > @@ -50,6 +50,7 @@ static struct clk_ops stub_clk_ops = { > > static const struct udevice_id stub_clk_ids[] = { > { .compatible = "qcom,rpmcc" }, > + { .compatible = "qcom,qcs615-rpmh-clk" }, > { .compatible = "qcom,sdm670-rpmh-clk" }, > { .compatible = "qcom,sdm845-rpmh-clk" }, > { .compatible = "qcom,sc7180-rpmh-clk" }, > @@ -69,4 +70,3 @@ U_BOOT_DRIVER(clk_stub) = { > .of_match = stub_clk_ids, > .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF, > }; > - > diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h > index 3a4550d8536..bc7e0453cba 100644 > --- a/drivers/clk/qcom/clock-qcom.h > +++ b/drivers/clk/qcom/clock-qcom.h > @@ -14,6 +14,7 @@ > #define CFG_CLK_SRC_GPLL0_AUX2 (2 << 8) > #define CFG_CLK_SRC_GPLL2 (2 << 8) > #define CFG_CLK_SRC_GPLL2_MAIN (2 << 8) > +#define CFG_CLK_SRC_GPLL6_OUT_MAIN (2 << 8) > #define CFG_CLK_SRC_GPLL9 (2 << 8) > #define CFG_CLK_SRC_GPLL0_ODD (3 << 8) > #define CFG_CLK_SRC_GPLL6 (4 << 8) > diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c > index 4700baba8c9..483642531ef 100644 > --- a/drivers/clk/qcom/clock-qcs615.c > +++ b/drivers/clk/qcom/clock-qcs615.c > @@ -18,6 +18,7 @@ > #define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf034 > #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c > #define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf060 > +#define SDCC1_APPS_CLK_CMD_RCGR 0x12028 > > #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) > #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) > @@ -52,6 +53,10 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate) > 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); > clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); > return rate; > + case GCC_SDCC1_APPS_CLK: > + clk_rcg_set_rate(priv->base, SDCC1_APPS_CLK_CMD_RCGR, > + 1, CFG_CLK_SRC_GPLL6_OUT_MAIN); > + return rate; > default: > return 0; > } > @@ -66,6 +71,11 @@ static const struct gate_clk qcs615_clks[] = { > GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)), > GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)), > GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)), > + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x12008, BIT(0)), > + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x12004, BIT(0)), > + GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x1200c, BIT(0)), > + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)), > + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)), > GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, > GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT), > GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, > GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT), > GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, > GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT), > -- > 2.34.1 >
