On Wed, 2026-01-28 at 17:56 +0530, Siddharth Vadapalli wrote: The $subject needs to be fixed. Sorry for accidentally sending the patch before fixing it.
I will post the v2 patch with the $subject fixed. Regards, Siddharth. > From: Bryan Brattlof <[email protected]> > > Moving forward, DM firmware will no longer mess with the MAIN_PLL3. > This means MAIN_PLL3 will need to be manually set to 2GHz in order for > the CPSW9G HSDIV to have the correct 250MHz output for RGMII. > > Signed-off-by: Bryan Brattlof <[email protected]> > Signed-off-by: Siddharth Vadapalli <[email protected]> > --- > > Hello, > > This patch is based on commit > 431f1ce46bb Revert a number of incorrect commits > of the master branch of U-Boot. > > Regards, > Siddharth. > > arch/arm/mach-k3/r5/j721e/clk-data.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-k3/r5/j721e/clk-data.c > b/arch/arm/mach-k3/r5/j721e/clk-data.c > index e4511092c86..bb7f61901b4 100644 > --- a/arch/arm/mach-k3/r5/j721e/clk-data.c > +++ b/arch/arm/mach-k3/r5/j721e/clk-data.c > @@ -539,7 +539,7 @@ static const struct clk_data clk_list[] = { > CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", > "main_pll_hfosc_sel_out2", 0x682000, 0), > CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", > "main_pll_hfosc_sel_out23", 0x697000, 0), > CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", > "main_pll25_hfosc_sel_out0", 0x699000, 0), > - CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", > "main_pll_hfosc_sel_out3", 0x683000, 0), > + CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", > "main_pll_hfosc_sel_out3", 0x683000, 0, 2000000000), > CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", > "main_pll_hfosc_sel_out5", 0x685000, 0), > CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", > "main_pll_hfosc_sel_out6", 0x686000, 0), > CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", > "main_pll_hfosc_sel_out7", 0x687000, 0),
