On Wed, Jan 28, 2026 at 12:13:12AM +0000, ChiaWei Wang wrote: > > From: Tom Rini <[email protected]> > > Sent: Wednesday, January 28, 2026 5:32 AM > > > > As of v2026.01, no platforms contain any rel.dyn sections in their xPL phase > > images. Their inclusion in linker scripts initially was an oversight as > > part of > > taking the full U-Boot linker scripts and modifying them down. Then in > > commit > > 8b0ebe054bb3 ("arm: Update linker scripts to ensure appended device tree is > > aligned") these sections were used to force correct alignment for the device > > tree. This however, lead to a different problem. > > > > That problem is that when we do not have a separate BSS section in SPL we > > instead would overlay the BSS with the rel.dyn section, in the common linker > > script case. This in turn lead to creating an incorrectly sized BSS "pad" > > file > > sometimes (depending on arbitrary changes within the rest of the binary > > itself). > > This in turn lead to the dtb being in the wrong location in the binary and > > not > > found at run time. > > > > This commit fixes a few things: > > - Remove the rel.dyn section from all ARM SPL linker scripts. > > - In turn, this moves the dtb alignment statement in to another section. > > - For ast2600 which uses CONFIG_POSITION_INDEPENDENT we need to keep > > the > > symbols however. > > > > Tested-by: Fabio Estevam <[email protected]> > > Reported-by: Fabio Estevam <[email protected]> > > Co-developed-by: Ilias Apalodimas <[email protected]> > > Signed-off-by: Tom Rini <[email protected]> > > --- > > I sent this off-list to Fabio first to confirm it finally fixed things. > > > > Cc: "Chia-Wei, Wang" <[email protected]> > > Cc: Adam Ford <[email protected]> > > --- > > arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 8 -------- > > arch/arm/cpu/u-boot-spl.lds | 13 ++----------- > > arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 16 +++++++--------- > > board/davinci/da8xxevm/u-boot-spl-da850evm.lds | 9 ++------- > > 4 files changed, 11 insertions(+), 35 deletions(-) > > > > diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds > > b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds > > index b4adae272eba..ac166d1d8526 100644 > > --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds > > +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds > > @@ -33,14 +33,6 @@ SECTIONS > > *(.data*) > > } > > > > - . = ALIGN(4); > > - > > - .rel.dyn : { > > - __rel_dyn_start = .; > > - *(.rel*) > > - __rel_dyn_end = .; > > - } > > - > > .bss : { > > . = ALIGN(4); > > __bss_start = .; > > diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index > > d780a5060774..c578c3ebf821 100644 > > --- a/arch/arm/cpu/u-boot-spl.lds > > +++ b/arch/arm/cpu/u-boot-spl.lds > > @@ -41,23 +41,14 @@ SECTIONS > > __binman_sym_start = .; > > KEEP(*(SORT(.binman_sym*))); > > __binman_sym_end = .; > > - } > > - > > - . = ALIGN(4); > > - > > - __image_copy_end = .; > > - > > - .rel.dyn : { > > - __rel_dyn_start = .; > > - *(.rel*) > > - __rel_dyn_end = .; > > . = ALIGN(8); > > } > > > > + __image_copy_end = .; > > _image_binary_end = .; > > _end = .; > > > > - .bss __rel_dyn_start (OVERLAY) : { > > + .bss : { > > __bss_start = .; > > *(.bss*) > > . = ALIGN(8); > > diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds > > b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds > > index c9664a6ce566..303ace2f61ca 100644 > > --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds > > +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds > > @@ -49,19 +49,17 @@ SECTIONS > > __binman_sym_start = .; > > KEEP(*(SORT(.binman_sym*))); > > __binman_sym_end = .; > > + . = ALIGN(8); > > } > .nor > > > > - . = ALIGN(4); > > + /* > > + * These platforms enable CONFIG_POSITION_INDEPENDENT and so need > > + * these names. The always however hold the same value. > > + */ > > + __rel_dyn_start = .; > > + __rel_dyn_end = .; > > > > __image_copy_end = .; > > - > > - .rel.dyn : { > > - __rel_dyn_start = .; > > - *(.rel*) > > - __rel_dyn_end = .; > > - . = ALIGN(8); > > - } > .nor > > - > > _end = .; > > _image_binary_end = .; > > > > Thanks for the fix. > Aspeed enables PIE mainly for the U-Boot execution. > For SPL, the symbols should be fine to be the same. > > Reviewed-by: "Chia-Wei, Wang" <[email protected]>
Thanks. Does SPL really execute from address 0x0 on this platform? What confused me for a moment when looking in to this is that we have a non-zero CONFIG_TEXT_BASE but CONFIG_SPL_TEXT_BASE=0x0 -- Tom
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