During probe, toggle the OSPI controller reset if CONFIG_ZYNQMP_FIRMWARE is enabled to guarantee the block starts from a clean state. Add the small delay and error handling around reset assert/deassert. This ensures the OSPI controller is reliably reset during probe on AMD FPGA platforms.
Signed-off-by: Padmarao Begari <[email protected]> --- drivers/spi/cadence_qspi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index d1404e13810..a29acf75abd 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -13,6 +13,7 @@ #include <spi.h> #include <spi-mem.h> #include <dm/device_compat.h> +#include <linux/delay.h> #include <linux/err.h> #include <linux/errno.h> #include <linux/io.h> @@ -257,6 +258,24 @@ static int cadence_spi_probe(struct udevice *bus) if (priv->resets) reset_deassert_bulk(priv->resets); + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && priv->resets) { + /* Assert ospi controller */ + ret = reset_assert(priv->resets->resets); + if (ret) { + dev_err(bus, "Failed to assert OSPI reset: %d\n", ret); + return ret; + } + + udelay(10); + + /* Deassert ospi controller */ + ret = reset_deassert(priv->resets->resets); + if (ret) { + dev_err(bus, "Failed to deassert OSPI reset: %d\n", ret); + return ret; + } + } + if (!priv->qspi_is_init) { cadence_qspi_apb_controller_init(priv); priv->qspi_is_init = 1; -- 2.34.1
