The DesignWare Cores Ethernet Quality-of-Service databook state that the descriptor address from the start to the end of the ring must not cross the 4GB boundary.
Use lower_32_bits() to write the lower 32 bits of descriptor addresses, including the 32-bit tail pointers, consistently. No functional change is intended. Signed-off-by: Jonas Karlman <[email protected]> --- drivers/net/dwc_eth_qos.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 551ee0ea6a02..74cdaa27644f 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -683,7 +683,6 @@ static int eqos_start(struct udevice *dev) int ret, i; ulong rate; u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; - ulong last_rx_desc; ulong desc_pad; ulong addr64; @@ -1019,8 +1018,8 @@ static int eqos_start(struct udevice *dev) * that's not distinguishable from none of the descriptors being * available. */ - last_rx_desc = (ulong)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX - 1, true); - writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); + addr64 = (ulong)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX - 1, true); + writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_tail_pointer); eqos->started = true; @@ -1116,8 +1115,8 @@ static int eqos_send(struct udevice *dev, void *packet, int length) tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; eqos->config->ops->eqos_flush_desc(tx_desc); - writel((ulong)eqos_get_desc(eqos, eqos->tx_desc_idx, false), - &eqos->dma_regs->ch0_txdesc_tail_pointer); + writel(lower_32_bits((ulong)eqos_get_desc(eqos, eqos->tx_desc_idx, false)), + &eqos->dma_regs->ch0_txdesc_tail_pointer); for (i = 0; i < 1000000; i++) { eqos->config->ops->eqos_inval_desc(tx_desc); @@ -1198,7 +1197,8 @@ static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; eqos->config->ops->eqos_flush_desc(rx_desc); } - writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); + writel(lower_32_bits((ulong)rx_desc), + &eqos->dma_regs->ch0_rxdesc_tail_pointer); } eqos->rx_desc_idx++; -- 2.52.0
