On Fri Jan 30, 2026 at 4:31 PM IST, Ssunk wrote: > This patch adds JEDEC IDs for Puyasemi PY25F512HB, PY25F01GHB, > PY25F512LC, and PY25F01GLC flash parts. > > site: https://www.puyasemi.com
A link to the datasheets and a reference to the "Table ID Definitions" would be helpful in cross-checking the correctness of the IDs. > > Signed-off-by: Ssunk <[email protected]> The patch doesn't apply cleanly, please rebase on master or next (as appropriate) for the next revision. > --- > drivers/mtd/spi/Kconfig | 6 ++++++ > drivers/mtd/spi/spi-nor-ids.c | 11 +++++++++++ > 2 files changed, 17 insertions(+) > > diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig > index a9617c6c58..c223862a46 100644 > --- a/drivers/mtd/spi/Kconfig > +++ b/drivers/mtd/spi/Kconfig > @@ -217,6 +217,12 @@ config SPI_FLASH_XTX > Add support for various XTX (XTX Technology Limited) > SPI flash chips (XT25xxx). > > +config SPI_FLASH_PUYASEMI > + bool "PUYASEMI SPI flash support" > + help > + Add support for various PUYASEMI (Puya Semiconductor (Shanghai) Co., > Ltd.) > + SPI flash chips (py25xxx) > + Can't this be included as part of the existing CONFIG_SPI_FLASH_PUYA which was added by the commit 5c73c05f20be ("mtd: spi-nor-ids: Add Puya Semiconductor chips description")? Nit: Would be nice to see new configs being added in alphabetical order in the Kconfig, though the order is not strictly followed currently :( > endif > > config SPI_FLASH_USE_4K_SECTORS > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > index 4b7b358eac..2e479ab8a1 100644 > --- a/drivers/mtd/spi/spi-nor-ids.c > +++ b/drivers/mtd/spi/spi-nor-ids.c > @@ -624,6 +624,17 @@ const struct flash_info spi_nor_ids[] = { > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_4B_OPCODES) }, > { INFO("xt25w01g", 0x0b651B, 0, 64 * 1024, 2048, > SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_4B_OPCODES) }, > +#endif > +#ifdef CONFIG_SPI_FLASH_PUYASEMI > + /* Puya Semiconductor (Shanghai) Co., Ltd */ > + { INFO("py25f512hb", 0x85231a, 0, 64 * 1024, 1024, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_4B_OPCODES) }, > + { INFO("py25f01ghb", 0x85231b, 0, 64 * 1024, 2048, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_4B_OPCODES) }, > + { INFO("py25f512lc", 0x85631a, 0, 64 * 1024, 1024, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_4B_OPCODES) }, > + { INFO("py25f01glc", 0x85631b, 0, 64 * 1024, 2048, > + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | > SPI_NOR_4B_OPCODES) }, > #endif > { }, > };
