From: Chris-QJ Chen <[email protected]> Add support for MT8195 pinctrl. The driver is based on the kernel one.
Signed-off-by: Chris-QJ Chen <[email protected]> Signed-off-by: Julien Stephan <[email protected]> --- Add MT8195 pinctrl driver, based on the kernel one --- drivers/pinctrl/mediatek/Kconfig | 4 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8195.c | 1079 +++++++++++++++++++++++++++++ 3 files changed, 1084 insertions(+) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 8a588d17c4b..1d4f65f1845 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -38,6 +38,10 @@ config PINCTRL_MT8188 bool "MT8188 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT8195 + bool "MT8195 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT8365 bool "MT8365 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index b9116c073ea..2de250194e1 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o +obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8195.c b/drivers/pinctrl/mediatek/pinctrl-mt8195.c new file mode 100644 index 00000000000..031ad5f6a8a --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8195.c @@ -0,0 +1,1079 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * The MT8195 driver based on Linux generic pinctrl binding. + * + * Copyright (C) 2026 MediaTek Inc. + * Author: Chris Chen <[email protected]> + */ +#include <dm.h> +#include "pinctrl-mtk-common.h" + +#define PIN_FIELD_IOCFG0(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, IOCFG0_BASE, _s_addr, _x_addrs, \ + _s_bit, _x_bits, 32, 0) + +#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 0) + +#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits) \ + PIN_FIELD_BASE_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +#define MT8195_TYPE0_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP0) + +#define MT8195_TYPE1_PIN(_number, _name) \ + MTK_TYPED_PIN(_number, _name, DRV_GRP4, IO_TYPE_GRP1) + +enum { + IOCFG0_BASE, + IOCFG_BM_BASE, + IOCFG_BL_BASE, + IOCFG_BR_BASE, + IOCFG_LM_BASE, + IOCFG_RB_BASE, + IOCFG_TL_BASE, + EINT_BASE, +}; + +static const char * const mt8195_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint", +}; + +static const struct mtk_pin_field_calc mt8195_pin_mode_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8195_pin_dir_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_di_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_do_range[] = { + PIN_FIELD_IOCFG0(0, 144, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x040, 0x10, 5, 1), + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x040, 0x10, 6, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x040, 0x10, 7, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x040, 0x10, 13, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x040, 0x10, 8, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x040, 0x10, 14, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x040, 0x10, 9, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x040, 0x10, 15, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x040, 0x10, 10, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x040, 0x10, 16, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x040, 0x10, 11, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x040, 0x10, 17, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x040, 0x10, 12, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x040, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x040, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x040, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x040, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x040, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x040, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x040, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x040, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x060, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x060, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x060, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x060, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x060, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x070, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x070, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x070, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x070, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x070, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x070, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x070, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x070, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x070, 0x10, 20, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x070, 0x10, 21, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x060, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x060, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x060, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x060, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x060, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x060, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x060, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x060, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x060, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x060, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x060, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x060, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x060, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x060, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x060, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x060, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x060, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x060, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x060, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x070, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x060, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x070, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x070, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x060, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x060, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x060, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x060, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x060, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x060, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x060, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x070, 0x10, 11, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x030, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x030, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x030, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x030, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x030, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x030, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x030, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x030, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x030, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x030, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x030, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x030, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x030, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x030, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x030, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x030, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x030, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x030, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x030, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x030, 0x10, 0, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x030, 0x10, 20, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x030, 0x10, 28, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x030, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x030, 0x10, 30, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x030, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x040, 0x10, 0, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x030, 0x10, 31, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x030, 0x10, 25, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x030, 0x10, 26, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x030, 0x10, 23, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x030, 0x10, 24, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x030, 0x10, 22, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x030, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x010, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x010, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x010, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x010, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x010, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x010, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x030, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x030, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x030, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x030, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x030, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x030, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x030, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x030, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x030, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x030, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x030, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x030, 0x10, 10, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x040, 0x10, 3, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x040, 0x10, 1, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x040, 0x10, 4, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x040, 0x10, 2, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x030, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x030, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x030, 0x10, 15, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x030, 0x10, 14, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x070, 0x10, 13, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x070, 0x10, 12, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x070, 0x10, 15, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x070, 0x10, 14, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x070, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x070, 0x10, 16, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x070, 0x10, 19, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x070, 0x10, 18, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0d0, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0d0, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0d0, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0d0, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0d0, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0d0, 0x10, 5, 1), + PINS_FIELD_BASE(6, 7, IOCFG_LM_BASE, 0x0d0, 0x10, 6, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0d0, 0x10, 12, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0d0, 0x10, 7, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0d0, 0x10, 13, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0d0, 0x10, 8, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0d0, 0x10, 14, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0d0, 0x10, 9, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0d0, 0x10, 15, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0d0, 0x10, 10, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0d0, 0x10, 16, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0d0, 0x10, 11, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x090, 0x10, 11, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x090, 0x10, 10, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x090, 0x10, 9, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x090, 0x10, 11, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x090, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x090, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x090, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x090, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x090, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x090, 0x10, 5, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x090, 0x10, 6, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x090, 0x10, 7, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x090, 0x10, 8, 1), + PINS_FIELD_BASE(31, 33, IOCFG_BM_BASE, 0x0f0, 0x10, 4, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x0f0, 0x10, 0, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x0f0, 0x10, 1, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x0f0, 0x10, 4, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x0f0, 0x10, 2, 1), + PINS_FIELD_BASE(38, 39, IOCFG_BM_BASE, 0x0f0, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x0f0, 0x10, 14, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x0f0, 0x10, 13, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x0f0, 0x10, 16, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x0f0, 0x10, 15, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x0f0, 0x10, 25, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x0f0, 0x10, 26, 1), + PINS_FIELD_BASE(46, 47, IOCFG_BM_BASE, 0x0f0, 0x10, 5, 1), + PINS_FIELD_BASE(48, 51, IOCFG_BM_BASE, 0x0f0, 0x10, 6, 1), + PINS_FIELD_BASE(52, 55, IOCFG_BM_BASE, 0x0f0, 0x10, 7, 1), + PINS_FIELD_BASE(56, 59, IOCFG_BM_BASE, 0x0f0, 0x10, 8, 1), + PINS_FIELD_BASE(60, 63, IOCFG_BM_BASE, 0x0f0, 0x10, 9, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x0f0, 0x10, 10, 1), + PINS_FIELD_BASE(65, 68, IOCFG_BM_BASE, 0x0f0, 0x10, 3, 1), + PINS_FIELD_BASE(69, 71, IOCFG_BM_BASE, 0x0f0, 0x10, 10, 1), + PINS_FIELD_BASE(72, 75, IOCFG_BM_BASE, 0x0f0, 0x10, 11, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x0f0, 0x10, 12, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0e0, 0x10, 0, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0e0, 0x10, 1, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0e0, 0x10, 6, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0e0, 0x10, 7, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0e0, 0x10, 8, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0e0, 0x10, 9, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0e0, 0x10, 10, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0e0, 0x10, 11, 1), + PINS_FIELD_BASE(85, 88, IOCFG_BR_BASE, 0x0e0, 0x10, 14, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0e0, 0x10, 2, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0e0, 0x10, 3, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0e0, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0e0, 0x10, 5, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0e0, 0x10, 12, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0e0, 0x10, 13, 1), + PINS_FIELD_BASE(95, 98, IOCFG_BR_BASE, 0x0e0, 0x10, 15, 1), + PINS_FIELD_BASE(99, 102, IOCFG_BR_BASE, 0x0e0, 0x10, 16, 1), + PINS_FIELD_BASE(103, 104, IOCFG_BR_BASE, 0x0e0, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PINS_FIELD_BASE(106, 107, IOCFG_BR_BASE, 0x0e0, 0x10, 17, 1), + PINS_FIELD_BASE(108, 109, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x070, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x070, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x070, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x070, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x070, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x070, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0c0, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0c0, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0c0, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0c0, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0c0, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0c0, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0c0, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0c0, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0c0, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0c0, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0c0, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0c0, 0x10, 10, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0e0, 0x10, 18, 1), + PINS_FIELD_BASE(129, 131, IOCFG_BR_BASE, 0x0e0, 0x10, 19, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0c0, 0x10, 13, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0c0, 0x10, 12, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0c0, 0x10, 15, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0c0, 0x10, 14, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x0f0, 0x10, 18, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x0f0, 0x10, 17, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x0f0, 0x10, 20, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x0f0, 0x10, 19, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x0f0, 0x10, 22, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x0f0, 0x10, 21, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x0f0, 0x10, 24, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x0f0, 0x10, 23, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pu_range[] = { + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x00a0, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x00a0, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x00b0, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pd_range[] = { + PIN_FIELD_BASE(6, 6, IOCFG_LM_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(7, 7, IOCFG_LM_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, IOCFG_BM_BASE, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(32, 32, IOCFG_BM_BASE, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, IOCFG_BM_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(38, 38, IOCFG_BM_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(39, 39, IOCFG_BM_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(46, 46, IOCFG_BM_BASE, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(47, 47, IOCFG_BM_BASE, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(48, 48, IOCFG_BM_BASE, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(49, 49, IOCFG_BM_BASE, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, IOCFG_BM_BASE, 0x0080, 0x10, 25, 1), + PIN_FIELD_BASE(51, 51, IOCFG_BM_BASE, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(52, 52, IOCFG_BM_BASE, 0x0080, 0x10, 26, 1), + PIN_FIELD_BASE(53, 53, IOCFG_BM_BASE, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(54, 54, IOCFG_BM_BASE, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(55, 55, IOCFG_BM_BASE, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(56, 56, IOCFG_BM_BASE, 0x0080, 0x10, 24, 1), + PIN_FIELD_BASE(57, 57, IOCFG_BM_BASE, 0x0080, 0x10, 29, 1), + PIN_FIELD_BASE(58, 58, IOCFG_BM_BASE, 0x0080, 0x10, 27, 1), + PIN_FIELD_BASE(59, 59, IOCFG_BM_BASE, 0x0080, 0x10, 30, 1), + PIN_FIELD_BASE(60, 60, IOCFG_BM_BASE, 0x0080, 0x10, 28, 1), + PIN_FIELD_BASE(61, 61, IOCFG_BM_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(62, 62, IOCFG_BM_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(63, 63, IOCFG_BM_BASE, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(65, 65, IOCFG_BM_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(66, 66, IOCFG_BM_BASE, 0x0080, 0x10, 31, 1), + PIN_FIELD_BASE(67, 67, IOCFG_BM_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(68, 68, IOCFG_BM_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(97, 97, IOCFG_BR_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(98, 98, IOCFG_BR_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(99, 99, IOCFG_BR_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(100, 100, IOCFG_BR_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, IOCFG_BR_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(102, 102, IOCFG_BR_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(103, 103, IOCFG_BR_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(108, 108, IOCFG_BR_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, IOCFG_BR_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(129, 129, IOCFG_BR_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(130, 130, IOCFG_BR_BASE, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x0090, 0x10, 19, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_pupd_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0060, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0060, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0060, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0060, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0060, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0060, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0060, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0060, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0060, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0060, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0060, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0060, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0050, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_r0_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0080, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0080, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0080, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0080, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0080, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0080, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0080, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0080, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0080, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0080, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0080, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0080, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0070, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_r1_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, IOCFG_BR_BASE, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(86, 86, IOCFG_BR_BASE, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(87, 87, IOCFG_BR_BASE, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(88, 88, IOCFG_BR_BASE, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(95, 95, IOCFG_BR_BASE, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(96, 96, IOCFG_BR_BASE, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(104, 104, IOCFG_BR_BASE, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(106, 106, IOCFG_BR_BASE, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(107, 107, IOCFG_BR_BASE, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x0080, 0x10, 10, 1), +}; + +static const struct mtk_pin_field_calc mt8195_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, IOCFG_LM_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(1, 1, IOCFG_LM_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(2, 2, IOCFG_LM_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(3, 3, IOCFG_LM_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(4, 4, IOCFG_LM_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(5, 5, IOCFG_LM_BASE, 0x000, 0x10, 15, 3), + PINS_FIELD_BASE(6, 7, IOCFG_LM_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(8, 8, IOCFG_LM_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(9, 9, IOCFG_LM_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(10, 10, IOCFG_LM_BASE, 0x010, 0x10, 9, 3), + PIN_FIELD_BASE(11, 11, IOCFG_LM_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(12, 12, IOCFG_LM_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(13, 13, IOCFG_LM_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(14, 14, IOCFG_LM_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(15, 15, IOCFG_LM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(16, 16, IOCFG_LM_BASE, 0x010, 0x10, 18, 3), + PIN_FIELD_BASE(17, 17, IOCFG_LM_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(18, 18, IOCFG_BL_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(19, 19, IOCFG_BL_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(20, 20, IOCFG_BL_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(21, 21, IOCFG_BL_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(22, 22, IOCFG_BL_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(23, 23, IOCFG_BL_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(24, 24, IOCFG_BL_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(25, 25, IOCFG_BL_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(26, 26, IOCFG_BL_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(27, 27, IOCFG_BL_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(28, 28, IOCFG_BL_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(29, 29, IOCFG_BL_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(30, 30, IOCFG_BL_BASE, 0x000, 0x10, 24, 3), + PINS_FIELD_BASE(31, 33, IOCFG_BM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(34, 34, IOCFG_BM_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(35, 35, IOCFG_BM_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(36, 36, IOCFG_BM_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(37, 37, IOCFG_BM_BASE, 0x010, 0x10, 21, 3), + PINS_FIELD_BASE(38, 39, IOCFG_BM_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(40, 40, IOCFG_BM_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(41, 41, IOCFG_BM_BASE, 0x010, 0x10, 24, 3), + PIN_FIELD_BASE(42, 42, IOCFG_BM_BASE, 0x020, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, IOCFG_BM_BASE, 0x020, 0x10, 0, 3), + PIN_FIELD_BASE(44, 44, IOCFG_BM_BASE, 0x030, 0x10, 0, 3), + PIN_FIELD_BASE(45, 45, IOCFG_BM_BASE, 0x030, 0x10, 3, 3), + PINS_FIELD_BASE(46, 47, IOCFG_BM_BASE, 0x010, 0x10, 3, 3), + PINS_FIELD_BASE(48, 51, IOCFG_BM_BASE, 0x010, 0x10, 6, 3), + PINS_FIELD_BASE(52, 55, IOCFG_BM_BASE, 0x010, 0x10, 9, 3), + PINS_FIELD_BASE(56, 59, IOCFG_BM_BASE, 0x010, 0x10, 12, 3), + PINS_FIELD_BASE(60, 63, IOCFG_BM_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(64, 64, IOCFG_BM_BASE, 0x010, 0x10, 18, 3), + PINS_FIELD_BASE(65, 68, IOCFG_BM_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(69, 69, IOCFG_BM_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(70, 70, IOCFG_BM_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(71, 71, IOCFG_BM_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(72, 72, IOCFG_BM_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(73, 73, IOCFG_BM_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(74, 74, IOCFG_BM_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, IOCFG_BM_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, IOCFG_BM_BASE, 0x010, 0x10, 18, 3), + PIN_FIELD_BASE(77, 77, IOCFG_BR_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(78, 78, IOCFG_BR_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(79, 79, IOCFG_BR_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(80, 80, IOCFG_BR_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(81, 81, IOCFG_BR_BASE, 0x000, 0x10, 28, 3), + PIN_FIELD_BASE(82, 82, IOCFG_BR_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(83, 83, IOCFG_BR_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(84, 84, IOCFG_BR_BASE, 0x010, 0x10, 3, 3), + PINS_FIELD_BASE(85, 88, IOCFG_BR_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(89, 89, IOCFG_BR_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(90, 90, IOCFG_BR_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(91, 91, IOCFG_BR_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(92, 92, IOCFG_BR_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(93, 93, IOCFG_BR_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(94, 94, IOCFG_BR_BASE, 0x010, 0x10, 9, 3), + PINS_FIELD_BASE(95, 98, IOCFG_BR_BASE, 0x010, 0x10, 18, 3), + PINS_FIELD_BASE(99, 102, IOCFG_BR_BASE, 0x010, 0x10, 21, 3), + PINS_FIELD_BASE(103, 104, IOCFG_BR_BASE, 0x010, 0x10, 24, 3), + PIN_FIELD_BASE(105, 105, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PINS_FIELD_BASE(106, 107, IOCFG_BR_BASE, 0x010, 0x10, 24, 3), + PINS_FIELD_BASE(108, 109, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PIN_FIELD_BASE(110, 110, IOCFG_RB_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(111, 111, IOCFG_RB_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(112, 112, IOCFG_RB_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(113, 113, IOCFG_RB_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(114, 114, IOCFG_RB_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(115, 115, IOCFG_RB_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(116, 116, IOCFG_TL_BASE, 0x000, 0x10, 27, 3), + PIN_FIELD_BASE(117, 117, IOCFG_TL_BASE, 0x000, 0x10, 24, 3), + PIN_FIELD_BASE(118, 118, IOCFG_TL_BASE, 0x000, 0x10, 21, 3), + PIN_FIELD_BASE(119, 119, IOCFG_TL_BASE, 0x000, 0x10, 18, 3), + PIN_FIELD_BASE(120, 120, IOCFG_TL_BASE, 0x010, 0x10, 3, 3), + PIN_FIELD_BASE(121, 121, IOCFG_TL_BASE, 0x000, 0x10, 3, 3), + PIN_FIELD_BASE(122, 122, IOCFG_TL_BASE, 0x000, 0x10, 0, 3), + PIN_FIELD_BASE(123, 123, IOCFG_TL_BASE, 0x000, 0x10, 15, 3), + PIN_FIELD_BASE(124, 124, IOCFG_TL_BASE, 0x000, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, IOCFG_TL_BASE, 0x000, 0x10, 9, 3), + PIN_FIELD_BASE(126, 126, IOCFG_TL_BASE, 0x000, 0x10, 6, 3), + PIN_FIELD_BASE(127, 127, IOCFG_TL_BASE, 0x010, 0x10, 0, 3), + PIN_FIELD_BASE(128, 128, IOCFG_BR_BASE, 0x010, 0x10, 27, 3), + PINS_FIELD_BASE(129, 130, IOCFG_BR_BASE, 0x020, 0x10, 0, 3), + PINS_FIELD_BASE(131, 131, IOCFG_BR_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, IOCFG_TL_BASE, 0x010, 0x10, 9, 3), + PIN_FIELD_BASE(133, 133, IOCFG_TL_BASE, 0x010, 0x10, 6, 3), + PIN_FIELD_BASE(134, 134, IOCFG_TL_BASE, 0x010, 0x10, 15, 3), + PIN_FIELD_BASE(135, 135, IOCFG_TL_BASE, 0x010, 0x10, 12, 3), + PIN_FIELD_BASE(136, 136, IOCFG_BM_BASE, 0x020, 0x10, 9, 3), + PIN_FIELD_BASE(137, 137, IOCFG_BM_BASE, 0x020, 0x10, 6, 3), + PIN_FIELD_BASE(138, 138, IOCFG_BM_BASE, 0x020, 0x10, 15, 3), + PIN_FIELD_BASE(139, 139, IOCFG_BM_BASE, 0x020, 0x10, 12, 3), + PIN_FIELD_BASE(140, 140, IOCFG_BM_BASE, 0x020, 0x10, 21, 3), + PIN_FIELD_BASE(141, 141, IOCFG_BM_BASE, 0x020, 0x10, 18, 3), + PIN_FIELD_BASE(142, 142, IOCFG_BM_BASE, 0x020, 0x10, 27, 3), + PIN_FIELD_BASE(143, 143, IOCFG_BM_BASE, 0x020, 0x10, 24, 3), +}; + +static const struct mtk_pin_reg_calc mt8195_reg_cals[] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8195_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8195_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8195_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8195_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8195_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8195_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8195_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8195_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8195_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8195_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8195_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8195_pin_r1_range), +}; + +static const struct mtk_pin_desc mt8195_pins[] = { + MT8195_TYPE1_PIN(0, "GPIO_00"), + MT8195_TYPE1_PIN(1, "GPIO_01"), + MT8195_TYPE1_PIN(2, "GPIO_02"), + MT8195_TYPE1_PIN(3, "GPIO_03"), + MT8195_TYPE1_PIN(4, "GPIO_04"), + MT8195_TYPE1_PIN(5, "GPIO_05"), + MT8195_TYPE0_PIN(6, "GPIO_06"), + MT8195_TYPE0_PIN(7, "GPIO_07"), + MT8195_TYPE0_PIN(8, "SDA0"), + MT8195_TYPE0_PIN(9, "SCL0"), + MT8195_TYPE0_PIN(10, "SDA1"), + MT8195_TYPE0_PIN(11, "SCL1"), + MT8195_TYPE0_PIN(12, "SDA2"), + MT8195_TYPE0_PIN(13, "SCL2"), + MT8195_TYPE0_PIN(14, "SDA3"), + MT8195_TYPE0_PIN(15, "SCL3"), + MT8195_TYPE0_PIN(16, "SDA4"), + MT8195_TYPE0_PIN(17, "SCL4"), + MT8195_TYPE0_PIN(18, "DPTX_HPD"), + MT8195_TYPE0_PIN(19, "PCIE_WAKE_N"), + MT8195_TYPE0_PIN(20, "PCIE_PERESET_N"), + MT8195_TYPE0_PIN(21, "PCIE_CLKREQ_N"), + MT8195_TYPE0_PIN(22, "CMMCLK0"), + MT8195_TYPE0_PIN(23, "CMMCLK1"), + MT8195_TYPE0_PIN(24, "CMMCLK2"), + MT8195_TYPE0_PIN(25, "CMMRST"), + MT8195_TYPE0_PIN(26, "CMMPDN"), + MT8195_TYPE0_PIN(27, "HDMIRX_HTPLG"), + MT8195_TYPE0_PIN(28, "HDMIRX_PWR5V"), + MT8195_TYPE0_PIN(29, "HDMIRX_SCL"), + MT8195_TYPE0_PIN(30, "HDMIRX_SDA"), + MT8195_TYPE0_PIN(31, "HDMITX_PWR5V"), + MT8195_TYPE0_PIN(32, "HDMITX_HTPLG"), + MT8195_TYPE0_PIN(33, "HDMITX_CEC"), + MT8195_TYPE0_PIN(34, "HDMITX_SCL"), + MT8195_TYPE0_PIN(35, "HDMITX_SDA"), + MT8195_TYPE0_PIN(36, "PMIC_RTC32K_CK"), + MT8195_TYPE0_PIN(37, "PMIC_WATCHDOG"), + MT8195_TYPE0_PIN(38, "PMIC_SRCLKEN_IN0"), + MT8195_TYPE0_PIN(39, "PMIC_SRCLKEN_IN1"), + MT8195_TYPE0_PIN(40, "PWRAP_SPI_CSN"), + MT8195_TYPE0_PIN(41, "PWRAP_SPI_CK"), + MT8195_TYPE0_PIN(42, "PWRAP_SPI_MO"), + MT8195_TYPE0_PIN(43, "PWRAP_SPI_MI"), + MT8195_TYPE0_PIN(44, "SPMI_M_SCL"), + MT8195_TYPE0_PIN(45, "SPMI_M_SDA"), + MT8195_TYPE0_PIN(46, "I2SIN_MCK"), + MT8195_TYPE0_PIN(47, "I2SIN_BCK"), + MT8195_TYPE0_PIN(48, "I2SIN_WS"), + MT8195_TYPE0_PIN(49, "I2SIN_D0"), + MT8195_TYPE0_PIN(50, "I2SO1_MCK"), + MT8195_TYPE0_PIN(51, "I2SO1_BCK"), + MT8195_TYPE0_PIN(52, "I2SO1_WS"), + MT8195_TYPE0_PIN(53, "I2SO1_D0"), + MT8195_TYPE0_PIN(54, "I2SO1_D1"), + MT8195_TYPE0_PIN(55, "I2SO1_D2"), + MT8195_TYPE0_PIN(56, "I2SO1_D3"), + MT8195_TYPE0_PIN(57, "I2SO2_MCK"), + MT8195_TYPE0_PIN(58, "I2SO2_BCK"), + MT8195_TYPE0_PIN(59, "I2SO2_WS"), + MT8195_TYPE0_PIN(60, "I2SO2_D0"), + MT8195_TYPE0_PIN(61, "DMIC1_SCK"), + MT8195_TYPE0_PIN(62, "DMIC1_DAT"), + MT8195_TYPE0_PIN(63, "DMIC2_SCK"), + MT8195_TYPE0_PIN(64, "DMIC2_DAT"), + MT8195_TYPE0_PIN(65, "PCM_DO"), + MT8195_TYPE0_PIN(66, "PCM_CLK"), + MT8195_TYPE0_PIN(67, "PCM_DI"), + MT8195_TYPE0_PIN(68, "PCM_SYNC"), + MT8195_TYPE0_PIN(69, "AUD_CLK_MOSI"), + MT8195_TYPE0_PIN(70, "AUD_SYNC_MOSI"), + MT8195_TYPE0_PIN(71, "AUD_DAT_MOSI0"), + MT8195_TYPE0_PIN(72, "AUD_DAT_MOSI1"), + MT8195_TYPE0_PIN(73, "AUD_DAT_MISO0"), + MT8195_TYPE0_PIN(74, "AUD_DAT_MISO1"), + MT8195_TYPE0_PIN(75, "AUD_DAT_MISO2"), + MT8195_TYPE0_PIN(76, "SCP_VREQ_VAO"), + MT8195_TYPE1_PIN(77, "DGI_D0"), + MT8195_TYPE1_PIN(78, "DGI_D1"), + MT8195_TYPE1_PIN(79, "DGI_D2"), + MT8195_TYPE1_PIN(80, "DGI_D3"), + MT8195_TYPE1_PIN(81, "DGI_D4"), + MT8195_TYPE1_PIN(82, "DGI_D5"), + MT8195_TYPE1_PIN(83, "DGI_D6"), + MT8195_TYPE1_PIN(84, "DGI_D7"), + MT8195_TYPE1_PIN(85, "DGI_D8"), + MT8195_TYPE1_PIN(86, "DGI_D9"), + MT8195_TYPE1_PIN(87, "DGI_D10"), + MT8195_TYPE1_PIN(88, "DGI_D11"), + MT8195_TYPE1_PIN(89, "DGI_D12"), + MT8195_TYPE1_PIN(90, "DGI_D13"), + MT8195_TYPE1_PIN(91, "DGI_D14"), + MT8195_TYPE1_PIN(92, "DGI_D15"), + MT8195_TYPE1_PIN(93, "DGI_HSYNC"), + MT8195_TYPE1_PIN(94, "DGI_VSYNC"), + MT8195_TYPE1_PIN(95, "DGI_DE"), + MT8195_TYPE1_PIN(96, "DGI_CK"), + MT8195_TYPE0_PIN(97, "DISP_PWM0"), + MT8195_TYPE0_PIN(98, "UART0_TXD"), + MT8195_TYPE0_PIN(99, "UART0_RXD"), + MT8195_TYPE0_PIN(100, "UART1_RTS"), + MT8195_TYPE0_PIN(101, "UART1_CTS"), + MT8195_TYPE0_PIN(102, "UART1_TXD"), + MT8195_TYPE0_PIN(103, "UART1_RXD"), + MT8195_TYPE1_PIN(104, "KPROW0"), + MT8195_TYPE1_PIN(105, "KPROW1"), + MT8195_TYPE1_PIN(106, "KPCOL0"), + MT8195_TYPE1_PIN(107, "KPCOL1"), + MT8195_TYPE0_PIN(108, "DSI_LCM_RST"), + MT8195_TYPE0_PIN(109, "DSI_DSI_TE"), + MT8195_TYPE1_PIN(110, "MSDC1_CMD"), + MT8195_TYPE1_PIN(111, "MSDC1_CLK"), + MT8195_TYPE1_PIN(112, "MSDC1_DAT0"), + MT8195_TYPE1_PIN(113, "MSDC1_DAT1"), + MT8195_TYPE1_PIN(114, "MSDC1_DAT2"), + MT8195_TYPE1_PIN(115, "MSDC1_DAT3"), + MT8195_TYPE1_PIN(116, "EMMC_DAT7"), + MT8195_TYPE1_PIN(117, "EMMC_DAT6"), + MT8195_TYPE1_PIN(118, "EMMC_DAT5"), + MT8195_TYPE1_PIN(119, "EMMC_DAT4"), + MT8195_TYPE1_PIN(120, "EMMC_RSTB"), + MT8195_TYPE1_PIN(121, "EMMC_CMD"), + MT8195_TYPE1_PIN(122, "EMMC_CLK"), + MT8195_TYPE1_PIN(123, "EMMC_DAT3"), + MT8195_TYPE1_PIN(124, "EMMC_DAT2"), + MT8195_TYPE1_PIN(125, "EMMC_DAT1"), + MT8195_TYPE1_PIN(126, "EMMC_DAT0"), + MT8195_TYPE1_PIN(127, "EMMC_DSL"), + MT8195_TYPE0_PIN(128, "USB_IDDIG"), + MT8195_TYPE0_PIN(129, "USB_DRV_VBUS"), + MT8195_TYPE0_PIN(130, "USB_IDDIG_1P"), + MT8195_TYPE0_PIN(131, "USB_DRV_VBUS_1P"), + MT8195_TYPE0_PIN(132, "SPIM0_CSB"), + MT8195_TYPE0_PIN(133, "SPIM0_CLK"), + MT8195_TYPE0_PIN(134, "SPIM0_MO"), + MT8195_TYPE0_PIN(135, "SPIM0_MI"), + MT8195_TYPE0_PIN(136, "SPIM1_CSB"), + MT8195_TYPE0_PIN(137, "SPIM1_CLK"), + MT8195_TYPE0_PIN(138, "SPIM1_MO"), + MT8195_TYPE0_PIN(139, "SPIM1_MI"), + MT8195_TYPE0_PIN(140, "SPIM2_CSB"), + MT8195_TYPE0_PIN(141, "SPIM2_CLK"), + MT8195_TYPE0_PIN(142, "SPIM2_MO"), + MT8195_TYPE0_PIN(143, "SPIM2_MI"), +}; + +static const struct mtk_io_type_desc mt8195_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "mt8195", + .bias_set = mtk_pinconf_bias_set_pu_pd, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, + [IO_TYPE_GRP1] = { + .name = "MSDC", + .bias_set = mtk_pinconf_bias_set_pupd_r1_r0, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +/* List all groups consisting of these pins dedicated to the enablement of + * certain hardware block and the corresponding mode for all of the pins. + * The hardware probably has multiple combinations of these pinouts. + */ + +/* UART0_0_RXD_TXD */ +static int mt8195_uart0_0_rxd_txd_pins[] = { 99, 98 }; +static int mt8195_uart0_0_rxd_txd_funcs[] = { 1, 1 }; +/* UART1_0 */ +static int mt8195_uart1_0_pins[] = { 103, 102 }; +static int mt8195_uart1_0_funcs[] = { 1, 1 }; +/* MSDC0 */ +static int mt8195_msdc0_pins[] = { 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126 }; +static int mt8195_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; +/* i2c0 */ +static int mt8195_i2c0_pins[] = { 8, 9 }; +static int mt8195_i2c0_funcs[] = { 1, 1 }; +/* i2c1 */ +static int mt8195_i2c1_pins[] = {10, 11 }; +static int mt8195_i2c1_funcs[] = { 1, 1 }; +/* i2c2 */ +static int mt8195_i2c2_pins[] = { 12, 13 }; +static int mt8195_i2c2_funcs[] = { 1, 1 }; +/* i2c3 */ +static int mt8195_i2c3_pins[] = { 14, 15 }; +static int mt8195_i2c3_funcs[] = { 1, 1 }; +/* i2c4 */ +static int mt8195_i2c4_pins[] = { 16, 17 }; +static int mt8195_i2c4_funcs[] = { 1, 1 }; +/* i2c5 */ +static int mt8195_i2c5_pins[] = { 30, 29 }; +static int mt8195_i2c5_funcs[] = { 3, 3 }; +/* i2c6 */ +static int mt8195_i2c6_pins[] = { 25, 26 }; +static int mt8195_i2c6_funcs[] = { 4, 4 }; +/* spi0 */ +static int mt8195_spi0_pins[] = { 132, 133, 134, 135 }; +static int mt8195_spi0_funcs[] = { 1, 1, 1, 1 }; +/* spi1 */ +static int mt8195_spi1_pins[] = { 136, 137, 138, 139 }; +static int mt8195_spi1_funcs[] = { 1, 1, 1, 1 }; +/* spi2 */ +static int mt8195_spi2_pins[] = { 140, 141, 142, 143 }; +static int mt8195_spi2_funcs[] = { 1, 1, 1, 1 }; + +static const struct mtk_group_desc mt8195_groups[] = { + PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8195_uart0_0_rxd_txd), + PINCTRL_PIN_GROUP("uart1_0", mt8195_uart1_0), + PINCTRL_PIN_GROUP("msdc0", mt8195_msdc0), + PINCTRL_PIN_GROUP("i2c0", mt8195_i2c0), + PINCTRL_PIN_GROUP("i2c1", mt8195_i2c1), + PINCTRL_PIN_GROUP("i2c2", mt8195_i2c2), + PINCTRL_PIN_GROUP("i2c3", mt8195_i2c3), + PINCTRL_PIN_GROUP("i2c4", mt8195_i2c4), + PINCTRL_PIN_GROUP("i2c5", mt8195_i2c5), + PINCTRL_PIN_GROUP("i2c6", mt8195_i2c6), + PINCTRL_PIN_GROUP("spi0", mt8195_spi0), + PINCTRL_PIN_GROUP("spi1", mt8195_spi1), + PINCTRL_PIN_GROUP("spi2", mt8195_spi2), +}; + +static const char *const mt8195_uart_groups[] = { + "uart0_0_rxd_txd", "uart1_0", +}; + +static const char *const mt8195_msdc_groups[] = { + "msdc0", +}; + +static const char *const mt8195_i2c_groups[] = { + "i2c0", "i2c1", "i2c2", "i2c3", "i2c4", "i2c5", "i2c6" +}; + +static const char *const mt8195_spi_groups[] = { + "spi0", "spi1", "spi2", +}; + +static const struct mtk_function_desc mt8195_functions[] = { + { "uart", mt8195_uart_groups, ARRAY_SIZE(mt8195_uart_groups) }, + { "msdc", mt8195_msdc_groups, ARRAY_SIZE(mt8195_msdc_groups) }, + { "i2c", mt8195_i2c_groups, ARRAY_SIZE(mt8195_i2c_groups) }, + { "spi", mt8195_spi_groups, ARRAY_SIZE(mt8195_spi_groups) }, +}; + +static struct mtk_pinctrl_soc mt8195_data = { + .name = "mt8195_pinctrl", + .reg_cal = mt8195_reg_cals, + .pins = mt8195_pins, + .npins = ARRAY_SIZE(mt8195_pins), + .grps = mt8195_groups, + .ngrps = ARRAY_SIZE(mt8195_groups), + .funcs = mt8195_functions, + .nfuncs = ARRAY_SIZE(mt8195_functions), + .io_type = mt8195_io_type_desc, + .ntype = ARRAY_SIZE(mt8195_io_type_desc), + .base_names = mt8195_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8195_pinctrl_register_base_names), + .base_calc = 1, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt8195_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8195_data); +} + +static const struct udevice_id mt8195_pctrl_match[] = { + { .compatible = "mediatek,mt8195-pinctrl" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(mt8195_pinctrl) = { + .name = "mt8195_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8195_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt8195_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; --- base-commit: eed514b11d04a2f8a949521ad3bffba3ec98bd2f change-id: 20260129-add-mt8195-pinctrl-driver-0f3432f96368 prerequisite-change-id: 20260129-add-mt8195-clock-support-727400553f87:v1 prerequisite-patch-id: 5dbe4461fa3456f3c7d80a7fa5a60d52bc719f65 prerequisite-patch-id: fac65a0526e9c15e8a4b3f81d85e61d1947dfe16 prerequisite-patch-id: 0d12fae50ce6da8dc7b0d978e4640431038d5904 Best regards, -- Julien Stephan <[email protected]>
