Update the DDR Configurations for AM62Px SK according to the SysConfig DDR Configuration tool v0.10.32. [1]
[1] https://dev.ti.com/tirex/content/Processor_DDR_Config_0.10.32.0000/docs/REVISION_HISTORY.html Signed-off-by: Santhosh Kumar K <[email protected]> --- arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi | 25 +++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi index c7e33ba50b99..763498df937b 100644 --- a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi +++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi @@ -1,19 +1,20 @@ // SPDX-License-Identifier: GPL-2.0+ /* * This file was generated with the - * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02 - * Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time) + * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.32 + * Fri Jan 30 2026 13:50:37 GMT+0530 (India Standard Time) * DDR Type: LPDDR4 * F0 = 50MHz F1 = NA F2 = 1600MHz * Density (per channel): 16Gb * Number of Ranks: 2 - */ +*/ #define DDRSS_PLL_FHS_CNT 5 #define DDRSS_PLL_FREQUENCY_1 800000000 #define DDRSS_PLL_FREQUENCY_2 800000000 #define DDRSS_SDRAM_IDX 17 #define DDRSS_REGION_IDX 17 +#define DDRSS_TOOL_VERSION "0.10.32" #define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -358,7 +359,7 @@ #define DDRSS_CTL_340_DATA 0x00000000 #define DDRSS_CTL_341_DATA 0x00000000 #define DDRSS_CTL_342_DATA 0x00000000 -#define DDRSS_CTL_343_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x7FFFFFFF #define DDRSS_CTL_344_DATA 0x00000000 #define DDRSS_CTL_345_DATA 0x00000000 #define DDRSS_CTL_346_DATA 0x00000000 @@ -375,14 +376,14 @@ #define DDRSS_CTL_357_DATA 0x00000000 #define DDRSS_CTL_358_DATA 0x00000000 #define DDRSS_CTL_359_DATA 0x00000000 -#define DDRSS_CTL_360_DATA 0x00000000 -#define DDRSS_CTL_361_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0xFFFFFFFF +#define DDRSS_CTL_361_DATA 0xFFFF0000 #define DDRSS_CTL_362_DATA 0x00000000 -#define DDRSS_CTL_363_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0xFFFFFFFF #define DDRSS_CTL_364_DATA 0x00000000 -#define DDRSS_CTL_365_DATA 0x00000000 -#define DDRSS_CTL_366_DATA 0x00000000 -#define DDRSS_CTL_367_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00FFFFFF +#define DDRSS_CTL_366_DATA 0xFFFF00FF +#define DDRSS_CTL_367_DATA 0x0000FFFF #define DDRSS_CTL_368_DATA 0x00000000 #define DDRSS_CTL_369_DATA 0x00000000 #define DDRSS_CTL_370_DATA 0x00000000 @@ -669,8 +670,8 @@ #define DDRSS_PI_216_DATA 0x01910100 #define DDRSS_PI_217_DATA 0x01000191 #define DDRSS_PI_218_DATA 0x01910191 -#define DDRSS_PI_219_DATA 0x32103200 -#define DDRSS_PI_220_DATA 0x01013210 +#define DDRSS_PI_219_DATA 0x301B3200 +#define DDRSS_PI_220_DATA 0x0101301B #define DDRSS_PI_221_DATA 0x0A070601 #define DDRSS_PI_222_DATA 0x180F090D #define DDRSS_PI_223_DATA 0x180F0911 -- 2.34.1
