From: Quentin Schulz <[email protected]> The ATAGS set by Rockchip DDR init blob[1] specify DRAM banks above the first addressable 4GiB which we haven't done in the mem_map for RK3588 yet.
For 4GiB DRAM, the 256MiB missing from the first addressable 4GiB (due to MMIO) are accessible at the end of the 8GiB address space. For 8GiB, 4-8GiB address space is used for the additional 4GiB and the missing 256MiB are at the end of 12GiB address space. For 12, 4-12GiB and the missing 256MiB at the end of 20GiB address space. For 16GiB, 4-~16GiB with two holes (reasons unknown) around 16GiB and the missing 256MiB is at the end of 20GiB address space. For 32GiB, 4-16~GiB with two holes and then 16GiB to 32GiB address space (so likely missing 256MiB from MMIO address space). [1] https://gist.github.com/Kwiboo/1c020d37e3adbc9d0d79dc003d921977 Suggested-by: Jonas Karlman <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> --- This is the RK3588 counterpart to RK3568's[1] which is required for Marek's patch[2] to not crash RK35xx series of SoCs when booting. This (plus patch[2]) has been tested on 4, 8 and 16GiB by TFTP'ing a kernel and DTB into the various DRAM regions above 4GiB and booting this kernel+dtb combination. Note that I have zero clue as to what this is actually doing as I cannot understand where this mem_map is actually used, hence the RFC. [1] https://lore.kernel.org/u-boot/[email protected]/ [2] https://lore.kernel.org/u-boot/[email protected]/ --- arch/arm/mach-rockchip/rk3588/rk3588.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index 55d2caab4fe..438642ca529 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -87,6 +87,24 @@ static struct mm_region rk3588_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = 0x2fc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x3fc500000UL, + .phys = 0x3fc500000UL, + .size = 0x3a00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { .virt = 0x900000000, .phys = 0x900000000, .size = 0x150000000, --- base-commit: 16fcbcb2ee25ea042c1e9cfbc04f7a5554746b64 change-id: 20260202-rk3588-mem-map-053661aa7e46 Best regards, -- Quentin Schulz <[email protected]>
