Add a new MUX_MIXED_CLR_SET_UPD_FLAGS() macro. This is the same as MUX_CLR_SET_UPD_FLAGS() except that it uses the parent_flags member of the union instead of parent.
This will be needed by the incoming mt8189 clock driver. Signed-off-by: David Lechner <[email protected]> --- drivers/clk/mediatek/clk-mtk.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index c6874445dbe..c4aeee49abd 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -221,6 +221,24 @@ struct mtk_composite { .flags = _flags, \ } +#define MUX_MIXED_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\ + _mux_clr_ofs, _shift, _width, _gate,\ + _upd_ofs, _upd, _flags) { \ + .id = _id, \ + .mux_reg = _mux_ofs, \ + .mux_set_reg = _mux_set_ofs, \ + .mux_clr_reg = _mux_clr_ofs, \ + .upd_reg = _upd_ofs, \ + .upd_shift = _upd, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_reg = _mux_ofs, \ + .gate_shift = _gate, \ + .parent_flags = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = CLK_PARENT_MIXED | (_flags), \ + } + struct mtk_gate_regs { u32 sta_ofs; u32 clr_ofs; -- 2.43.0
