On 6/2/2026 3:17 am, Sune Brian wrote:
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On Tue, Jan 27, 2026 at 4:03 PM Chee, Tien Fong
<[email protected]> wrote:
On 16/12/2025 4:46 pm, [email protected] wrote:
From: Alif Zakuan Yuslaimi <[email protected]>
Add DRAM size checking compare between size from device tree and actual
hardware.
Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.
get_ram_size() uses size from device tree. So, it has consistency with
other device families.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
---
drivers/ddr/altera/sdram_gen5.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index 7a0a043557b..d5892850da7 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -6,6 +6,7 @@
#include <dm.h>
#include <errno.h>
#include <div64.h>
+#include <hang.h>
#include <init.h>
#include <log.h>
#include <ram.h>
@@ -615,6 +616,22 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
sdram_size = sdram_calculate_size(sdr_ctrl);
debug("SDRAM: %ld MiB\n", sdram_size >> 20);
+ /* setup the dram info within bd */
+ dram_init_banksize();
+
+ if (sdram_size != gd->bd->bi_dram[0].size) {
+ printf("DDR: Warning: DRAM size from device tree (%d MiB)\n",
+ (u32)(gd->bd->bi_dram[0].size >> 20));
+ printf(" mismatch with hardware (%d MiB).\n",
+ (u32)(sdram_size >> 20));
+ }
+
+ if (gd->bd->bi_dram[0].size > sdram_size) {
+ printf("DDR: Error: DRAM size from device tree is greater\n");
+ printf(" than hardware size.\n");
+ hang();
+ }
+
if (sdram_is_ecc_enabled(sdr_ctrl)) {
/* Must set USEECCASDATA to 0 if ECC is enabled */
clrbits_le32(&sdr_ctrl->static_cfg,
@@ -623,7 +640,8 @@ static int altera_gen5_sdram_probe(struct udevice *dev)
}
/* Sanity check ensure correct SDRAM size specified */
- if (get_ram_size(0, sdram_size) != sdram_size) {
+ if (get_ram_size(0, gd->bd->bi_dram[0].size) !=
+ gd->bd->bi_dram[0].size) {
puts("SDRAM size check failed!\n");
goto failed;
}
Reviewed-by: Tien Fong Chee <[email protected]>
Hi T.F. and Alif,
I know you reviewed the code.
But I am not sure on 2GB w/o ECC run it will pass SPL stage.
However when applied to the patch 2GB w/ ECC it does not pass SPL.
I would like to confirm that ARM GDB cannot be used to test ECC or not?
As I do see it involved D-Cache on
"drivers/ddr/altera/sdram_soc32.c"
Thanks,
Brian
Hi Brian,
The code has been tested with RAM boot via ARM debugger on our Cyclone V
SOC Development Board with ECC enabled, we are able to boot up to Linux
successfully.
Our board specs can be found here -
https://www.rocketboards.org/foswiki/Documentation/AlteraSoCDevelopmentBoard
You can also refer our documentation here on running U-Boot with ARM
debugger -
https://altera-fpga.github.io/rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/#appendix-2-run-u-boot-with-the-debugger-from-command-line
Thanks,
Alif
Best regards,
Tien Fong
