On Wed, 28 Jan 2026 18:06:21 +0530, Siddharth Vadapalli wrote: > Moving forward, DM firmware will no longer mess with the MAIN_PLL3. > This means MAIN_PLL3 will need to be manually set to 2GHz in order for > the CPSW9G HSDIV to have the correct 250MHz output for RGMII. > >
Applied to u-boot/master, thanks!
[1/1] arm: mach-k3: r5: j721e: clk-data: manually set the main_pll3 frequency
commit: da6d5a93ddac5e60ebc84c75456318fa20a8f995
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Tom
