From: Bo-Chen Chen <[email protected]> Add pinctrl support for mt8189.
Signed-off-by: Bo-Chen Chen <[email protected]> Co-developed-by: David Lechner <[email protected]> Signed-off-by: David Lechner <[email protected]> --- drivers/pinctrl/mediatek/Kconfig | 4 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8189.c | 1276 +++++++++++++++++++++++++++++ 3 files changed, 1281 insertions(+) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 8a588d17c4b..ca6980c7a77 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -38,6 +38,10 @@ config PINCTRL_MT8188 bool "MT8188 SoC pinctrl driver" select PINCTRL_MTK +config PINCTRL_MT8189 + bool "MT8189 SoC pinctrl driver" + select PINCTRL_MTK + config PINCTRL_MT8365 bool "MT8365 SoC pinctrl driver" select PINCTRL_MTK diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index b9116c073ea..c61e13dfeb8 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o obj-$(CONFIG_PINCTRL_MT7987) += pinctrl-mt7987.o obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o obj-$(CONFIG_PINCTRL_MT8188) += pinctrl-mt8188.o +obj-$(CONFIG_PINCTRL_MT8189) += pinctrl-mt8189.o obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8189.c b/drivers/pinctrl/mediatek/pinctrl-mt8189.c new file mode 100644 index 00000000000..b798f3c019b --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8189.c @@ -0,0 +1,1276 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 MediaTek Inc. + * Author: Bo-Chen Chen <[email protected]> + */ +#include <dm.h> +#include "pinctrl-mtk-common.h" + +enum { + IO_BASE, + IO_BASE_LM, + IO_BASE_RB0, + IO_BASE_RB1, + IO_BASE_BM0, + IO_BASE_BM1, + IO_BASE_BM2, + IO_BASE_LT0, + IO_BASE_LT1, + IO_BASE_RT, + IO_BASE_EINT0, + IO_BASE_EINT1, + IO_BASE_EINT2, + IO_BASE_EINT3, + IO_BASE_EINT4, +}; + +#define PIN_FIELD_IOCFG0(s_pin, e_pin, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_BASE_CALC(s_pin, e_pin, IO_BASE, s_addr, x_addrs, s_bit, \ + x_bits, 32, 0) + +#define PIN_FIELD_BASE(pin, i_base, s_addr, s_bit, x_bits) \ + PIN_FIELD_BASE_CALC(pin, pin, i_base, s_addr, 0x10, s_bit, x_bits, \ + 32, 0) + +static const struct mtk_pin_field_calc mt8189_pin_mode_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8189_pin_dir_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0000, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_di_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_do_range[] = { + PIN_FIELD_IOCFG0(0, 182, 0x0100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_smt_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x00e0, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x00c0, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x00c0, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x00c0, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x00c0, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x00c0, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x00e0, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x00e0, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x00e0, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x00e0, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x00e0, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x00e0, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00e0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00e0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x00f0, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x00f0, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00e0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00e0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x00e0, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x00e0, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x00e0, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x00e0, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x00f0, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x00f0, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x00f0, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x00c0, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x00c0, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00e0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00e0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x00c0, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00e0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x00f0, 19, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x00c0, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x00f0, 21, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x00f0, 20, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x00f0, 23, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x00f0, 22, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x00f0, 25, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x00f0, 24, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x00f0, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x00f0, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x00f0, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x00f0, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x00f0, 6, 1), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00e0, 20, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00e0, 21, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00e0, 22, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00e0, 23, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x00c0, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x00c0, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x00c0, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x00c0, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x00c0, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x00c0, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x00c0, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x00c0, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x00c0, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00e0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00e0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00e0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00e0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00e0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00e0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00e0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00e0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x00f0, 10, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x00f0, 12, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x00f0, 11, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x00f0, 13, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00e0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00e0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00e0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00e0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00e0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00e0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x00f0, 13, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00e0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x00c0, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x00c0, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x00c0, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x00c0, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00e0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00e0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00e0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x00e0, 24, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x00e0, 25, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x00e0, 26, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x00e0, 27, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0120, 20, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0120, 19, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0120, 22, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0120, 21, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0120, 16, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0120, 17, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0120, 23, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0120, 15, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0120, 18, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0120, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0120, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0120, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0120, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0120, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0120, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x00e0, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x00e0, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x00e0, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x00e0, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x00e0, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x00e0, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x00e0, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x00e0, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x00e0, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x00c0, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x00c0, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x00c0, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00e0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00e0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00e0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00e0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x00c0, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x00c0, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x00c0, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x00c0, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x00c0, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x00c0, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x00c0, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x00c0, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x00c0, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x00c0, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x00c0, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x00c0, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x00c0, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x00c0, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x00c0, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x00c0, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x00c0, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x00c0, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00e0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00e0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x00c0, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x00c0, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x00c0, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x00c0, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x00c0, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x00c0, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x00c0, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x00c0, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x00c0, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x00c0, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x00c0, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x00f0, 14, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x00c0, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x00f0, 15, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x00f0, 16, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x00f0, 17, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x00f0, 18, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0120, 12, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0120, 11, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0120, 10, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0090, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0120, 14, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0120, 7, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0120, 6, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0090, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0120, 9, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0120, 8, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0090, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0120, 13, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00f0, 8, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00f0, 7, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00f0, 9, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00f0, 10, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00f0, 11, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00f0, 12, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00f0, 5, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00f0, 4, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00f0, 6, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00f0, 7, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00f0, 8, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00f0, 9, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0120, 24, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0120, 25, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x00f0, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_ies_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0050, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0050, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0050, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0050, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0050, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0050, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0050, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0050, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0050, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0050, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0050, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0050, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x0070, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x0070, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0050, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0050, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x0070, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x0070, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0050, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0050, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0050, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0050, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0040, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0040, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0040, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0050, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0050, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x0070, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x0070, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0050, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x0070, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0050, 19, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0050, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0050, 21, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0050, 20, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0050, 23, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0050, 22, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0050, 25, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0050, 24, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0050, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0050, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0050, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0050, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0050, 6, 1), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0050, 20, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0050, 21, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0050, 22, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0050, 23, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0050, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0050, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0050, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0050, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0050, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0050, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0050, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0050, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0050, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x0070, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x0070, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x0070, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x0070, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x0070, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x0070, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x0070, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x0070, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0040, 10, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0040, 12, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0040, 11, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0040, 13, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x0070, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x0070, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x0070, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x0070, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x0070, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x0070, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0050, 13, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x0070, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0050, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0050, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0050, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0050, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x0070, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x0070, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x0070, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0050, 24, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0050, 25, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0050, 26, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0050, 27, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0060, 20, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0060, 19, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0060, 22, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0060, 21, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0060, 16, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0060, 17, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0060, 23, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0060, 15, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0060, 18, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0060, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0060, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0060, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0060, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0060, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0060, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0050, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0050, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0050, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0050, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0050, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0050, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0050, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0050, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0050, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0050, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0050, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0050, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x0070, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x0070, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x0070, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x0070, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0050, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0050, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0050, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0050, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0050, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0050, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0050, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0050, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0050, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0050, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0050, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0050, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0050, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0050, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0050, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0050, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0050, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0050, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x0070, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x0070, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0050, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0050, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0050, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0050, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0050, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0050, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0050, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0050, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0050, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0050, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0050, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0050, 14, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0050, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0050, 15, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0050, 16, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0050, 17, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0050, 18, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0060, 12, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0060, 11, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0060, 10, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0020, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0060, 14, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0060, 7, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0060, 6, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0020, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0060, 9, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0060, 8, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0020, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0060, 13, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0050, 8, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0050, 7, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0050, 9, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0050, 10, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0050, 11, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0050, 12, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0040, 5, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0040, 4, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0040, 6, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0040, 7, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0040, 8, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0040, 9, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0060, 24, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0060, 25, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0040, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pupd_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0090, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0090, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0090, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0090, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00a0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00a0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00a0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0050, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00a0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00a0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00a0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0050, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00a0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00a0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0050, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00a0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0090, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0090, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0090, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0090, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0090, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0090, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0080, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0080, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0080, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0080, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0080, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0080, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_r0_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00b0, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00b0, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00b0, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00b0, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00c0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00c0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00c0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0060, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00c0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00c0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00c0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0060, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00c0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00c0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0060, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00c0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00b0, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00b0, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00b0, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00b0, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00b0, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00b0, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00a0, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00a0, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00a0, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00a0, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00a0, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00a0, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_r1_range[] = { + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x00c0, 0, 1), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x00c0, 1, 1), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x00c0, 2, 1), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x00c0, 3, 1), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x00d0, 6, 1), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x00d0, 5, 1), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x00d0, 4, 1), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0070, 2, 1), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x00d0, 8, 1), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x00d0, 1, 1), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x00d0, 0, 1), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0070, 1, 1), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x00d0, 3, 1), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x00d0, 2, 1), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0070, 0, 1), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x00d0, 7, 1), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x00c0, 1, 1), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x00c0, 0, 1), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x00c0, 2, 1), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x00c0, 3, 1), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x00c0, 4, 1), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x00c0, 5, 1), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x00b0, 1, 1), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x00b0, 0, 1), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x00b0, 2, 1), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x00b0, 3, 1), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x00b0, 4, 1), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x00b0, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pu_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x00a0, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0090, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0090, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0090, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0090, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0090, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x00a0, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x00a0, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x00a0, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x00a0, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x00a0, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x00a0, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00b0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00b0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x00a0, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x00a0, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00b0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00b0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x00a0, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x00a0, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x00a0, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x00a0, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0090, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0090, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0090, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0090, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0090, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00b0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00b0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0090, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00b0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x00a0, 13, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0090, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x00a0, 15, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x00a0, 14, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x00a0, 17, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x00a0, 16, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x00a0, 19, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x00a0, 18, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x00a0, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x00a0, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x00a0, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x00a0, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x00a0, 6, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0090, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0090, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0090, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0090, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0090, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0090, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0090, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0090, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0090, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00b0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00b0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00b0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00b0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00b0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00b0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00b0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00b0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0090, 4, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0090, 6, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0090, 5, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0090, 7, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00b0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00b0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00b0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00b0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00b0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00b0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x00a0, 7, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00b0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0090, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0090, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0090, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0090, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00b0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00b0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00b0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x00a0, 22, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x00a0, 23, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x00a0, 24, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x00a0, 25, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x00b0, 11, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x00b0, 10, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x00b0, 13, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x00b0, 12, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x00b0, 7, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x00b0, 8, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x00b0, 14, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x00b0, 6, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x00b0, 9, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x00b0, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x00b0, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x00b0, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x00b0, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x00b0, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x00b0, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x00a0, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x00a0, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x00a0, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x00a0, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x00a0, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x00a0, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x00a0, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x00a0, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x00a0, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0090, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0090, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0090, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00b0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00b0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00b0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00b0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0090, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0090, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0090, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0090, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0090, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0090, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0090, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0090, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0090, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0090, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0090, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0090, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0090, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0090, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0090, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0090, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0090, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0090, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00b0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00b0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0090, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0090, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0090, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0090, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0090, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0090, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0090, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0090, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0090, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0090, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0090, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x00a0, 8, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0090, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x00a0, 9, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x00a0, 10, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x00a0, 11, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x00a0, 12, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x00b0, 15, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x00b0, 16, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0090, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_pd_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0080, 5, 1), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0080, 3, 1), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0080, 4, 1), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0080, 5, 1), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0080, 6, 1), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0080, 7, 1), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0080, 6, 1), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0080, 7, 1), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0080, 8, 1), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0080, 9, 1), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0080, 10, 1), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0080, 11, 1), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x00a0, 5, 1), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x00a0, 6, 1), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0080, 0, 1), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0080, 1, 1), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x00a0, 7, 1), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x00a0, 8, 1), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0080, 0, 1), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0080, 2, 1), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0080, 1, 1), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0080, 3, 1), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0070, 0, 1), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0070, 1, 1), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0070, 2, 1), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0080, 2, 1), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0080, 1, 1), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x00a0, 1, 1), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x00a0, 2, 1), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0080, 0, 1), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x00a0, 0, 1), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0080, 13, 1), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0080, 30, 1), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0080, 15, 1), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0080, 14, 1), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0080, 17, 1), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0080, 16, 1), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0080, 19, 1), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0080, 18, 1), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0080, 5, 1), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0080, 2, 1), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0080, 3, 1), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0080, 4, 1), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0080, 6, 1), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0080, 5, 1), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0080, 4, 1), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0080, 3, 1), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0080, 8, 1), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0080, 10, 1), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0080, 9, 1), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0080, 11, 1), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0080, 6, 1), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0080, 7, 1), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x00a0, 13, 1), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x00a0, 17, 1), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x00a0, 14, 1), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x00a0, 18, 1), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x00a0, 15, 1), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x00a0, 19, 1), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x00a0, 16, 1), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x00a0, 20, 1), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0070, 4, 1), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0070, 6, 1), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0070, 5, 1), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0070, 7, 1), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x00a0, 22, 1), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x00a0, 21, 1), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x00a0, 24, 1), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x00a0, 23, 1), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x00a0, 26, 1), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x00a0, 25, 1), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0080, 7, 1), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x00a0, 27, 1), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0080, 13, 1), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0080, 12, 1), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0080, 15, 1), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0080, 14, 1), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x00a0, 29, 1), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x00a0, 28, 1), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x00a0, 30, 1), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0080, 22, 1), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0080, 23, 1), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0080, 24, 1), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0080, 25, 1), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0090, 11, 1), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0090, 10, 1), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0090, 13, 1), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0090, 12, 1), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0090, 7, 1), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0090, 8, 1), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0090, 14, 1), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0090, 6, 1), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0090, 9, 1), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0090, 0, 1), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0090, 5, 1), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0090, 3, 1), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0090, 4, 1), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0090, 1, 1), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0090, 2, 1), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0080, 15, 1), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0080, 12, 1), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0080, 14, 1), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0080, 13, 1), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0080, 19, 1), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0080, 16, 1), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0080, 18, 1), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0080, 17, 1), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0080, 4, 1), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0080, 0, 1), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0080, 1, 1), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0080, 2, 1), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x00a0, 9, 1), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x00a0, 12, 1), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x00a0, 10, 1), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x00a0, 11, 1), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0080, 26, 1), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0080, 25, 1), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0080, 24, 1), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0080, 23, 1), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0080, 19, 1), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0080, 18, 1), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0080, 17, 1), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0080, 16, 1), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0080, 22, 1), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0080, 15, 1), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0080, 20, 1), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0080, 27, 1), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0080, 13, 1), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0080, 14, 1), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0080, 28, 1), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0080, 21, 1), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0080, 11, 1), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0080, 12, 1), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x00a0, 3, 1), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x00a0, 4, 1), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0080, 3, 1), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0080, 4, 1), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0080, 0, 1), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0080, 1, 1), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0080, 2, 1), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0080, 5, 1), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0080, 6, 1), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0080, 7, 1), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0080, 8, 1), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0080, 9, 1), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0080, 10, 1), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0080, 8, 1), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0080, 29, 1), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0080, 9, 1), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0080, 10, 1), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0080, 11, 1), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0080, 12, 1), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0090, 15, 1), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0090, 16, 1), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0070, 3, 1), +}; + +static const struct mtk_pin_field_calc mt8189_pin_drv_range[] = { + PIN_FIELD_BASE(0, IO_BASE_RB0, 0x0000, 15, 3), + PIN_FIELD_BASE(1, IO_BASE_RB1, 0x0000, 9, 3), + PIN_FIELD_BASE(2, IO_BASE_RB1, 0x0000, 12, 3), + PIN_FIELD_BASE(3, IO_BASE_RB1, 0x0000, 15, 3), + PIN_FIELD_BASE(4, IO_BASE_RB1, 0x0000, 18, 3), + PIN_FIELD_BASE(5, IO_BASE_RB1, 0x0000, 21, 3), + PIN_FIELD_BASE(6, IO_BASE_RB0, 0x0000, 18, 3), + PIN_FIELD_BASE(7, IO_BASE_RB0, 0x0000, 21, 3), + PIN_FIELD_BASE(8, IO_BASE_RB0, 0x0000, 24, 3), + PIN_FIELD_BASE(9, IO_BASE_RB0, 0x0000, 27, 3), + PIN_FIELD_BASE(10, IO_BASE_RB0, 0x0010, 0, 3), + PIN_FIELD_BASE(11, IO_BASE_RB0, 0x0010, 3, 3), + PIN_FIELD_BASE(12, IO_BASE_BM1, 0x0000, 15, 3), + PIN_FIELD_BASE(13, IO_BASE_BM1, 0x0000, 18, 3), + PIN_FIELD_BASE(14, IO_BASE_BM2, 0x0000, 0, 3), + PIN_FIELD_BASE(15, IO_BASE_BM2, 0x0000, 3, 3), + PIN_FIELD_BASE(16, IO_BASE_BM1, 0x0000, 21, 3), + PIN_FIELD_BASE(17, IO_BASE_BM1, 0x0000, 24, 3), + PIN_FIELD_BASE(18, IO_BASE_RB0, 0x0000, 0, 3), + PIN_FIELD_BASE(19, IO_BASE_RB0, 0x0000, 6, 3), + PIN_FIELD_BASE(20, IO_BASE_RB0, 0x0000, 3, 3), + PIN_FIELD_BASE(21, IO_BASE_RB0, 0x0000, 9, 3), + PIN_FIELD_BASE(22, IO_BASE_RT, 0x0000, 0, 3), + PIN_FIELD_BASE(23, IO_BASE_RT, 0x0000, 3, 3), + PIN_FIELD_BASE(24, IO_BASE_RT, 0x0000, 6, 3), + PIN_FIELD_BASE(25, IO_BASE_LM, 0x0000, 6, 3), + PIN_FIELD_BASE(26, IO_BASE_LM, 0x0000, 3, 3), + PIN_FIELD_BASE(27, IO_BASE_BM1, 0x0000, 3, 3), + PIN_FIELD_BASE(28, IO_BASE_BM1, 0x0000, 6, 3), + PIN_FIELD_BASE(29, IO_BASE_LM, 0x0000, 0, 3), + PIN_FIELD_BASE(30, IO_BASE_BM1, 0x0000, 0, 3), + PIN_FIELD_BASE(31, IO_BASE_BM2, 0x0010, 27, 3), + PIN_FIELD_BASE(32, IO_BASE_BM0, 0x0030, 0, 3), + PIN_FIELD_BASE(33, IO_BASE_BM2, 0x0020, 3, 3), + PIN_FIELD_BASE(34, IO_BASE_BM2, 0x0020, 0, 3), + PIN_FIELD_BASE(35, IO_BASE_BM2, 0x0020, 9, 3), + PIN_FIELD_BASE(36, IO_BASE_BM2, 0x0020, 6, 3), + PIN_FIELD_BASE(37, IO_BASE_BM2, 0x0020, 15, 3), + PIN_FIELD_BASE(38, IO_BASE_BM2, 0x0020, 12, 3), + PIN_FIELD_BASE(39, IO_BASE_BM2, 0x0000, 15, 3), + PIN_FIELD_BASE(40, IO_BASE_BM2, 0x0000, 6, 3), + PIN_FIELD_BASE(41, IO_BASE_BM2, 0x0000, 9, 3), + PIN_FIELD_BASE(42, IO_BASE_BM2, 0x0000, 12, 3), + PIN_FIELD_BASE(43, IO_BASE_BM2, 0x0000, 18, 3), + PIN_FIELD_BASE(44, IO_BASE_RB0, 0x0020, 0, 3), + PIN_FIELD_BASE(45, IO_BASE_RB0, 0x0020, 3, 3), + PIN_FIELD_BASE(46, IO_BASE_RB0, 0x0020, 6, 3), + PIN_FIELD_BASE(47, IO_BASE_RB0, 0x0020, 9, 3), + PIN_FIELD_BASE(48, IO_BASE_LM, 0x0000, 15, 3), + PIN_FIELD_BASE(49, IO_BASE_LM, 0x0000, 12, 3), + PIN_FIELD_BASE(50, IO_BASE_LM, 0x0000, 9, 3), + PIN_FIELD_BASE(51, IO_BASE_RB1, 0x0000, 24, 3), + PIN_FIELD_BASE(52, IO_BASE_RB1, 0x0010, 0, 3), + PIN_FIELD_BASE(53, IO_BASE_RB1, 0x0000, 27, 3), + PIN_FIELD_BASE(54, IO_BASE_RB1, 0x0010, 3, 3), + PIN_FIELD_BASE(55, IO_BASE_LM, 0x0000, 18, 3), + PIN_FIELD_BASE(56, IO_BASE_LM, 0x0000, 21, 3), + PIN_FIELD_BASE(57, IO_BASE_BM1, 0x0010, 9, 3), + PIN_FIELD_BASE(58, IO_BASE_BM1, 0x0010, 21, 3), + PIN_FIELD_BASE(59, IO_BASE_BM1, 0x0010, 12, 3), + PIN_FIELD_BASE(60, IO_BASE_BM1, 0x0010, 24, 3), + PIN_FIELD_BASE(61, IO_BASE_BM1, 0x0010, 15, 3), + PIN_FIELD_BASE(62, IO_BASE_BM1, 0x0010, 27, 3), + PIN_FIELD_BASE(63, IO_BASE_BM1, 0x0010, 18, 3), + PIN_FIELD_BASE(64, IO_BASE_BM1, 0x0020, 0, 3), + PIN_FIELD_BASE(65, IO_BASE_RT, 0x0010, 0, 3), + PIN_FIELD_BASE(66, IO_BASE_RT, 0x0010, 6, 3), + PIN_FIELD_BASE(67, IO_BASE_RT, 0x0010, 3, 3), + PIN_FIELD_BASE(68, IO_BASE_RT, 0x0010, 9, 3), + PIN_FIELD_BASE(69, IO_BASE_BM1, 0x0020, 6, 3), + PIN_FIELD_BASE(70, IO_BASE_BM1, 0x0020, 3, 3), + PIN_FIELD_BASE(71, IO_BASE_BM1, 0x0020, 12, 3), + PIN_FIELD_BASE(72, IO_BASE_BM1, 0x0020, 9, 3), + PIN_FIELD_BASE(73, IO_BASE_BM1, 0x0020, 18, 3), + PIN_FIELD_BASE(74, IO_BASE_BM1, 0x0020, 15, 3), + PIN_FIELD_BASE(75, IO_BASE_BM2, 0x0010, 9, 3), + PIN_FIELD_BASE(76, IO_BASE_BM1, 0x0020, 21, 3), + PIN_FIELD_BASE(77, IO_BASE_RB1, 0x0010, 9, 3), + PIN_FIELD_BASE(78, IO_BASE_RB1, 0x0010, 6, 3), + PIN_FIELD_BASE(79, IO_BASE_RB1, 0x0010, 15, 3), + PIN_FIELD_BASE(80, IO_BASE_RB1, 0x0010, 12, 3), + PIN_FIELD_BASE(81, IO_BASE_BM1, 0x0020, 27, 3), + PIN_FIELD_BASE(82, IO_BASE_BM1, 0x0020, 24, 3), + PIN_FIELD_BASE(83, IO_BASE_BM1, 0x0030, 0, 3), + PIN_FIELD_BASE(84, IO_BASE_RB0, 0x0020, 12, 3), + PIN_FIELD_BASE(85, IO_BASE_RB0, 0x0020, 15, 3), + PIN_FIELD_BASE(86, IO_BASE_RB0, 0x0020, 18, 3), + PIN_FIELD_BASE(87, IO_BASE_RB0, 0x0020, 21, 3), + PIN_FIELD_BASE(88, IO_BASE_LT0, 0x0020, 0, 3), + PIN_FIELD_BASE(89, IO_BASE_LT0, 0x0010, 27, 3), + PIN_FIELD_BASE(90, IO_BASE_LT0, 0x0020, 6, 3), + PIN_FIELD_BASE(91, IO_BASE_LT0, 0x0020, 3, 3), + PIN_FIELD_BASE(92, IO_BASE_LT0, 0x0010, 18, 3), + PIN_FIELD_BASE(93, IO_BASE_LT0, 0x0010, 21, 3), + PIN_FIELD_BASE(94, IO_BASE_LT0, 0x0020, 9, 3), + PIN_FIELD_BASE(95, IO_BASE_LT0, 0x0010, 15, 3), + PIN_FIELD_BASE(96, IO_BASE_LT0, 0x0010, 24, 3), + PIN_FIELD_BASE(97, IO_BASE_LT0, 0x0000, 0, 3), + PIN_FIELD_BASE(98, IO_BASE_LT0, 0x0000, 15, 3), + PIN_FIELD_BASE(99, IO_BASE_LT0, 0x0000, 9, 3), + PIN_FIELD_BASE(100, IO_BASE_LT0, 0x0000, 12, 3), + PIN_FIELD_BASE(101, IO_BASE_LT0, 0x0000, 3, 3), + PIN_FIELD_BASE(102, IO_BASE_LT0, 0x0000, 6, 3), + PIN_FIELD_BASE(103, IO_BASE_RB0, 0x0010, 15, 3), + PIN_FIELD_BASE(104, IO_BASE_RB0, 0x0010, 6, 3), + PIN_FIELD_BASE(105, IO_BASE_RB0, 0x0010, 12, 3), + PIN_FIELD_BASE(106, IO_BASE_RB0, 0x0010, 9, 3), + PIN_FIELD_BASE(107, IO_BASE_RB0, 0x0010, 27, 3), + PIN_FIELD_BASE(108, IO_BASE_RB0, 0x0010, 18, 3), + PIN_FIELD_BASE(109, IO_BASE_RB0, 0x0010, 24, 3), + PIN_FIELD_BASE(110, IO_BASE_RB0, 0x0010, 21, 3), + PIN_FIELD_BASE(111, IO_BASE_RB0, 0x0000, 12, 3), + PIN_FIELD_BASE(112, IO_BASE_RB1, 0x0000, 0, 3), + PIN_FIELD_BASE(113, IO_BASE_RB1, 0x0000, 3, 3), + PIN_FIELD_BASE(114, IO_BASE_RB1, 0x0000, 6, 3), + PIN_FIELD_BASE(115, IO_BASE_BM1, 0x0000, 27, 3), + PIN_FIELD_BASE(116, IO_BASE_BM1, 0x0010, 6, 3), + PIN_FIELD_BASE(117, IO_BASE_BM1, 0x0010, 0, 3), + PIN_FIELD_BASE(118, IO_BASE_BM1, 0x0010, 3, 3), + PIN_FIELD_BASE(119, IO_BASE_BM0, 0x0020, 18, 3), + PIN_FIELD_BASE(120, IO_BASE_BM0, 0x0020, 15, 3), + PIN_FIELD_BASE(121, IO_BASE_BM0, 0x0020, 12, 3), + PIN_FIELD_BASE(122, IO_BASE_BM0, 0x0020, 9, 3), + PIN_FIELD_BASE(123, IO_BASE_BM0, 0x0010, 27, 3), + PIN_FIELD_BASE(124, IO_BASE_BM0, 0x0010, 24, 3), + PIN_FIELD_BASE(125, IO_BASE_BM0, 0x0010, 21, 3), + PIN_FIELD_BASE(126, IO_BASE_BM0, 0x0010, 18, 3), + PIN_FIELD_BASE(127, IO_BASE_BM0, 0x0020, 6, 3), + PIN_FIELD_BASE(128, IO_BASE_BM0, 0x0010, 15, 3), + PIN_FIELD_BASE(129, IO_BASE_BM0, 0x0020, 0, 3), + PIN_FIELD_BASE(130, IO_BASE_BM0, 0x0020, 21, 3), + PIN_FIELD_BASE(131, IO_BASE_BM0, 0x0010, 9, 3), + PIN_FIELD_BASE(132, IO_BASE_BM0, 0x0010, 12, 3), + PIN_FIELD_BASE(133, IO_BASE_BM0, 0x0020, 24, 3), + PIN_FIELD_BASE(134, IO_BASE_BM0, 0x0020, 3, 3), + PIN_FIELD_BASE(135, IO_BASE_BM0, 0x0010, 3, 3), + PIN_FIELD_BASE(136, IO_BASE_BM0, 0x0010, 6, 3), + PIN_FIELD_BASE(137, IO_BASE_BM1, 0x0000, 9, 3), + PIN_FIELD_BASE(138, IO_BASE_BM1, 0x0000, 12, 3), + PIN_FIELD_BASE(139, IO_BASE_BM0, 0x0000, 9, 3), + PIN_FIELD_BASE(140, IO_BASE_BM0, 0x0000, 12, 3), + PIN_FIELD_BASE(141, IO_BASE_BM0, 0x0000, 0, 3), + PIN_FIELD_BASE(142, IO_BASE_BM0, 0x0000, 3, 3), + PIN_FIELD_BASE(143, IO_BASE_BM0, 0x0000, 6, 3), + PIN_FIELD_BASE(144, IO_BASE_BM0, 0x0000, 15, 3), + PIN_FIELD_BASE(145, IO_BASE_BM0, 0x0000, 18, 3), + PIN_FIELD_BASE(146, IO_BASE_BM0, 0x0000, 21, 3), + PIN_FIELD_BASE(147, IO_BASE_BM0, 0x0000, 24, 3), + PIN_FIELD_BASE(148, IO_BASE_BM0, 0x0000, 27, 3), + PIN_FIELD_BASE(149, IO_BASE_BM0, 0x0010, 0, 3), + PIN_FIELD_BASE(150, IO_BASE_BM2, 0x0010, 12, 3), + PIN_FIELD_BASE(151, IO_BASE_BM0, 0x0020, 27, 3), + PIN_FIELD_BASE(152, IO_BASE_BM2, 0x0010, 15, 3), + PIN_FIELD_BASE(153, IO_BASE_BM2, 0x0010, 18, 3), + PIN_FIELD_BASE(154, IO_BASE_BM2, 0x0010, 21, 3), + PIN_FIELD_BASE(155, IO_BASE_BM2, 0x0010, 24, 3), + PIN_FIELD_BASE(156, IO_BASE_LT0, 0x0010, 6, 3), + PIN_FIELD_BASE(157, IO_BASE_LT0, 0x0010, 3, 3), + PIN_FIELD_BASE(158, IO_BASE_LT0, 0x0010, 0, 3), + PIN_FIELD_BASE(159, IO_BASE_LT1, 0x0000, 6, 3), + PIN_FIELD_BASE(160, IO_BASE_LT0, 0x0010, 12, 3), + PIN_FIELD_BASE(161, IO_BASE_LT0, 0x0000, 21, 3), + PIN_FIELD_BASE(162, IO_BASE_LT0, 0x0000, 18, 3), + PIN_FIELD_BASE(163, IO_BASE_LT1, 0x0000, 3, 3), + PIN_FIELD_BASE(164, IO_BASE_LT0, 0x0000, 27, 3), + PIN_FIELD_BASE(165, IO_BASE_LT0, 0x0000, 24, 3), + PIN_FIELD_BASE(166, IO_BASE_LT1, 0x0000, 0, 3), + PIN_FIELD_BASE(167, IO_BASE_LT0, 0x0010, 9, 3), + PIN_FIELD_BASE(168, IO_BASE_BM2, 0x0000, 24, 3), + PIN_FIELD_BASE(169, IO_BASE_BM2, 0x0000, 21, 3), + PIN_FIELD_BASE(170, IO_BASE_BM2, 0x0000, 27, 3), + PIN_FIELD_BASE(171, IO_BASE_BM2, 0x0010, 0, 3), + PIN_FIELD_BASE(172, IO_BASE_BM2, 0x0010, 3, 3), + PIN_FIELD_BASE(173, IO_BASE_BM2, 0x0010, 6, 3), + PIN_FIELD_BASE(174, IO_BASE_RT, 0x0000, 15, 3), + PIN_FIELD_BASE(175, IO_BASE_RT, 0x0000, 12, 3), + PIN_FIELD_BASE(176, IO_BASE_RT, 0x0000, 18, 3), + PIN_FIELD_BASE(177, IO_BASE_RT, 0x0000, 21, 3), + PIN_FIELD_BASE(178, IO_BASE_RT, 0x0000, 24, 3), + PIN_FIELD_BASE(179, IO_BASE_RT, 0x0000, 27, 3), + PIN_FIELD_BASE(180, IO_BASE_LT0, 0x0020, 12, 3), + PIN_FIELD_BASE(181, IO_BASE_LT0, 0x0020, 15, 3), + PIN_FIELD_BASE(182, IO_BASE_RT, 0x0000, 9, 3), +}; + +static const struct mtk_pin_reg_calc mt8189_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8189_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8189_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8189_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8189_pin_do_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8189_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8189_pin_ies_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8189_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8189_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8189_pin_r1_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8189_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8189_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8189_pin_drv_range), +}; + +static const char * const mt8189_pinctrl_register_base_names[] = { + [IO_BASE] = "base", + [IO_BASE_LM] = "lm", + [IO_BASE_RB0] = "rb0", + [IO_BASE_RB1] = "rb1", + [IO_BASE_BM0] = "bm0", + [IO_BASE_BM1] = "bm1", + [IO_BASE_BM2] = "bm2", + [IO_BASE_LT0] = "lt0", + [IO_BASE_LT1] = "lt1", + [IO_BASE_RT] = "rt", + [IO_BASE_EINT0] = "eint0", + [IO_BASE_EINT1] = "eint1", + [IO_BASE_EINT2] = "eint2", + [IO_BASE_EINT3] = "eint3", + [IO_BASE_EINT4] = "eint4", +}; + +static const struct mtk_pin_desc mt8189_pins[] = { + MTK_TYPED_PIN(0, "GPIO00", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(1, "GPIO01", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(2, "GPIO02", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(3, "GPIO03", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(4, "GPIO04", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(5, "GPIO05", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(6, "GPIO06", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(7, "GPIO07", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(8, "GPIO08", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(9, "GPIO09", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(10, "GPIO10", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(11, "GPIO11", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(12, "GPIO12", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(13, "GPIO13", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(14, "GPIO14", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(15, "GPIO15", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(16, "GPIO16", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(17, "GPIO17", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(18, "GPIO18", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(19, "GPIO19", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(20, "GPIO20", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(21, "GPIO21", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(22, "GPIO22", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(23, "GPIO23", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(24, "GPIO24", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(25, "GPIO25", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(26, "GPIO26", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(27, "GPIO27", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(28, "GPIO28", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(29, "GPIO29", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(30, "GPIO30", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(31, "GPIO31", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(32, "GPIO32", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(33, "GPIO33", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(34, "GPIO34", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(35, "GPIO35", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(36, "GPIO36", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(37, "GPIO37", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(38, "GPIO38", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(39, "GPIO39", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(40, "GPIO40", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(41, "GPIO41", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(42, "GPIO42", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(43, "GPIO43", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(44, "GPIO44", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(45, "GPIO45", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(46, "GPIO46", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(47, "GPIO47", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(48, "GPIO48", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(49, "GPIO49", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(50, "GPIO50", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(51, "GPIO51", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(52, "GPIO52", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(53, "GPIO53", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(54, "GPIO54", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(55, "GPIO55", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(56, "GPIO56", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(57, "GPIO57", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(58, "GPIO58", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(59, "GPIO59", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(60, "GPIO60", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(61, "GPIO61", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(62, "GPIO62", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(63, "GPIO63", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(64, "GPIO64", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(65, "GPIO65", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(66, "GPIO66", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(67, "GPIO67", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(68, "GPIO68", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(69, "GPIO69", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(70, "GPIO70", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(71, "GPIO71", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(72, "GPIO72", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(73, "GPIO73", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(74, "GPIO74", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(75, "GPIO75", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(76, "GPIO76", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(77, "GPIO77", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(78, "GPIO78", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(79, "GPIO79", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(80, "GPIO80", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(81, "GPIO81", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(82, "GPIO82", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(83, "GPIO83", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(84, "GPIO84", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(85, "GPIO85", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(86, "GPIO86", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(87, "GPIO87", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(88, "GPIO88", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(89, "GPIO89", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(90, "GPIO90", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(91, "GPIO91", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(92, "GPIO92", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(93, "GPIO93", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(94, "GPIO94", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(95, "GPIO95", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(96, "GPIO96", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(97, "GPIO97", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(98, "GPIO98", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(99, "GPIO99", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(100, "GPIO100", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(101, "GPIO101", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(102, "GPIO102", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(103, "GPIO103", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(104, "GPIO104", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(105, "GPIO105", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(106, "GPIO106", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(107, "GPIO107", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(108, "GPIO108", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(109, "GPIO109", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(110, "GPIO110", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(111, "GPIO111", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(112, "GPIO112", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(113, "GPIO113", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(114, "GPIO114", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(115, "GPIO115", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(116, "GPIO116", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(117, "GPIO117", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(118, "GPIO118", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(119, "GPIO119", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(120, "GPIO120", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(121, "GPIO121", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(122, "GPIO122", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(123, "GPIO123", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(124, "GPIO124", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(125, "GPIO125", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(126, "GPIO126", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(127, "GPIO127", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(128, "GPIO128", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(129, "GPIO129", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(130, "GPIO130", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(131, "GPIO131", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(132, "GPIO132", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(133, "GPIO133", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(134, "GPIO134", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(135, "GPIO135", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(136, "GPIO136", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(137, "GPIO137", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(138, "GPIO138", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(139, "GPIO139", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(140, "GPIO140", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(141, "GPIO141", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(142, "GPIO142", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(143, "GPIO143", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(144, "GPIO144", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(145, "GPIO145", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(146, "GPIO146", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(147, "GPIO147", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(148, "GPIO148", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(149, "GPIO149", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(150, "GPIO150", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(151, "GPIO151", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(152, "GPIO152", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(153, "GPIO153", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(154, "GPIO154", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(155, "GPIO155", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(156, "GPIO156", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(157, "GPIO157", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(158, "GPIO158", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(159, "GPIO159", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(160, "GPIO160", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(161, "GPIO161", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(162, "GPIO162", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(163, "GPIO163", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(164, "GPIO164", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(165, "GPIO165", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(166, "GPIO166", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(167, "GPIO167", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(168, "GPIO168", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(169, "GPIO169", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(170, "GPIO170", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(171, "GPIO171", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(172, "GPIO172", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(173, "GPIO173", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(174, "GPIO174", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(175, "GPIO175", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(176, "GPIO176", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(177, "GPIO177", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(178, "GPIO178", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(179, "GPIO179", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(180, "GPIO180", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(181, "GPIO181", DRV_GRP4, DRV_GRP0), + MTK_TYPED_PIN(182, "GPIO182", DRV_GRP4, DRV_GRP0), +}; + +static const struct mtk_io_type_desc mt8189_io_type_desc[] = { + [IO_TYPE_GRP0] = { + .name = "mt8189", + .bias_set = mtk_pinconf_bias_set_v1, + .drive_set = mtk_pinconf_drive_set_v1, + .input_enable = mtk_pinconf_input_enable_v1, + }, +}; + +static struct mtk_pinctrl_soc mt8189_data = { + .name = "mt8189_pinctrl", + .reg_cal = mt8189_reg_cals, + .pins = mt8189_pins, + .npins = ARRAY_SIZE(mt8189_pins), + .io_type = mt8189_io_type_desc, + .ntype = ARRAY_SIZE(mt8189_io_type_desc), + .base_names = mt8189_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8189_pinctrl_register_base_names), + .base_calc = 1, + .rev = MTK_PINCTRL_V1, +}; + +static int mtk_pinctrl_mt8189_probe(struct udevice *dev) +{ + return mtk_pinctrl_common_probe(dev, &mt8189_data); +} + +static const struct udevice_id mt8189_pctrl_match[] = { + { .compatible = "mediatek,mt8189-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(mt8189_pinctrl) = { + .name = "mt8189_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = mt8189_pctrl_match, + .ops = &mtk_pinctrl_ops, + .probe = mtk_pinctrl_mt8189_probe, + .priv_auto = sizeof(struct mtk_pinctrl_priv), +}; -- 2.43.0
