On 3/2/2026 3:59 pm, [email protected] wrote:
From: Alif Zakuan Yuslaimi <[email protected]>
AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.
Update the clock driver to explicitly exclude this clock ID from
enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id()
and treating this as a no-op in the socfpga_clk_enable() and
socfpga_clk_disable() functions.
This prevents unnecessary register access for clocks that cannot be gated
and ensures clean handling when the clock is present in the device tree.
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
---
drivers/clk/altera/clk-agilex.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c
index fdbf834bb2f..88423292c0b 100644
--- a/drivers/clk/altera/clk-agilex.c
+++ b/drivers/clk/altera/clk-agilex.c
@@ -728,6 +728,8 @@ static int bitmask_from_clk_id(struct clk *clk)
plat->pllgrp = CLKMGR_PERPLL_EN;
plat->bitmask = CLKMGR_PERPLLGRP_EN_NANDCLK_MASK;
break;
+ case AGILEX_L4_SYS_FREE_CLK:
+ return -EOPNOTSUPP;
default:
return -ENXIO;
}
@@ -742,6 +744,9 @@ static int socfpga_clk_enable(struct clk *clk)
int ret;
ret = bitmask_from_clk_id(clk);
+ if (ret == -EOPNOTSUPP)
+ return 0;
+
if (ret)
return ret;
@@ -757,6 +762,9 @@ static int socfpga_clk_disable(struct clk *clk)
int ret;
ret = bitmask_from_clk_id(clk);
+ if (ret == -EOPNOTSUPP)
+ return 0;
+
if (ret)
return ret;
Reviewed-by: Tien Fong Chee <[email protected]>
Best regards,
Tien Fong
