From: Raymond Mao <[email protected]> Add SPL support featuring debug UART output for early boot diagnostics on K1 SoC.
Signed-off-by: Raymond Mao <[email protected]> --- arch/riscv/cpu/k1/Kconfig | 2 ++ arch/riscv/dts/Makefile | 1 + arch/riscv/dts/k1-spl.dts | 25 +++++++++++++++++++++++++ arch/riscv/dts/k1.dtsi | 2 +- board/spacemit/k1/Makefile | 2 ++ board/spacemit/k1/spl.c | 24 ++++++++++++++++++++++++ configs/spacemit_k1_defconfig | 21 ++++++++++++++++++++- include/configs/k1.h | 7 +++++-- 8 files changed, 80 insertions(+), 4 deletions(-) create mode 100644 arch/riscv/dts/k1-spl.dts create mode 100644 board/spacemit/k1/spl.c diff --git a/arch/riscv/cpu/k1/Kconfig b/arch/riscv/cpu/k1/Kconfig index 4b621158334..011fc89557e 100644 --- a/arch/riscv/cpu/k1/Kconfig +++ b/arch/riscv/cpu/k1/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # # Copyright (C) 2024, Kongyang Liu <[email protected]> +# Copyright (C) 2025-2026, RISCstar Ltd. if ARCH_K1 @@ -9,6 +10,7 @@ config SPACEMIT_K1 select BINMAN select ARCH_EARLY_INIT_R select SYS_CACHE_SHIFT_6 + select SUPPORT_SPL imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 9b347fc3b50..e942ef95142 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_ARCH_K1) += k1-spl.dtb dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_ANDES_VOYAGER) += qilai-voyager.dtb dtb-$(CONFIG_TARGET_BANANAPI_F3) += k1-bananapi-f3.dtb diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1-spl.dts new file mode 100644 index 00000000000..c7196c2d722 --- /dev/null +++ b/arch/riscv/dts/k1-spl.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (C) 2023-2026 Spacemit, Inc + * Copyright (C) 2025-2026 RISCstar Ltd. + */ + +/dts-v1/; +#include "k1.dtsi" +#include "binman.dtsi" + +/ { + model = "spacemit k1 spl"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&soc { + bootph-all; + serial@d4017000 { + status = "okay"; + bootph-pre-ram; + }; +}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi index a633e43da32..9c203eb4b79 100644 --- a/arch/riscv/dts/k1.dtsi +++ b/arch/riscv/dts/k1.dtsi @@ -318,7 +318,7 @@ }; }; - soc { + soc: soc { compatible = "simple-bus"; interrupt-parent = <&plic>; #address-cells = <2>; diff --git a/board/spacemit/k1/Makefile b/board/spacemit/k1/Makefile index 2168698402b..f9cbf4b0e06 100644 --- a/board/spacemit/k1/Makefile +++ b/board/spacemit/k1/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # # Copyright (c) 2024, Kongyang Liu <[email protected]> +# Copyright (c) 2025-2026, RISCstar Ltd. obj-y := board.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c new file mode 100644 index 00000000000..e15cf5f1abf --- /dev/null +++ b/board/spacemit/k1/spl.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2025-2026, RISCstar Ltd. + */ + +#include <spl.h> + +void board_init_f(ulong dummy) +{ + int ret; + + ret = spl_early_init(); + if (ret) + panic("spl_early_init() failed:%d\n", ret); + + riscv_cpu_setup(); + + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_NONE; +} diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig index 0bdc3c800f0..d794170bc5b 100644 --- a/configs/spacemit_k1_defconfig +++ b/configs/spacemit_k1_defconfig @@ -3,7 +3,19 @@ CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000 -CONFIG_DEFAULT_DEVICE_TREE="k1-bananapi-f3" +CONFIG_DEFAULT_DEVICE_TREE="k1-spl" +CONFIG_SPL=y +CONFIG_SPL_TEXT_BASE=0xc0801000 +CONFIG_SPL_MAX_SIZE=0x33000 +CONFIG_SPL_BSS_START_ADDR=0xc0837000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_STACK=0xc0840000 +CONFIG_SPL_SIZE_LIMIT=0x31000 +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x08000000 +CONFIG_STACK_SIZE=0x100000 CONFIG_SYS_BOOTM_LEN=0xa000000 CONFIG_SYS_LOAD_ADDR=0x200000 CONFIG_ARCH_RV64I=y @@ -23,3 +35,10 @@ CONFIG_PINCTRL_SINGLE=y CONFIG_RESET_SPACEMIT_K1=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xd4017000 +CONFIG_DEBUG_UART_CLOCK=14700000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_NS16550=y +CONFIG_DEBUG_UART_ANNOUNCE=y +# CONFIG_DEBUG_SBI_CONSOLE is not set diff --git a/include/configs/k1.h b/include/configs/k1.h index 97cf4d72df0..e0b05c50b70 100644 --- a/include/configs/k1.h +++ b/include/configs/k1.h @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2024, Kongyang Liu <[email protected]> + * Copyright (C) 2025-2026, RISCstar Ltd. * */ #ifndef __CONFIG_H #define __CONFIG_H -#define CFG_SYS_SDRAM_BASE 0x0 -#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ +#define CFG_SYS_SDRAM_BASE 0x0 + +#define CFG_SYS_NS16550_CLK 14700000 +#define CFG_SYS_NS16550_IER 0x40 /* UART Unit Enable */ #endif /* __CONFIG_H */ -- 2.25.1
