Hi Tom,
please pull these 4 fixes to master branch.
Thanks,
Michal
The following changes since commit b99da05e1538b8fa153322da82917af2aa27e1d6:
Prepare v2026.04-rc2 (2026-02-09 15:07:50 -0600)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
tags/xilinx-for-v2026.04-rc3
for you to fetch changes up to ce6fc049b700894b2a8f25778103cf4f2d29cb34:
net: phy: mscc: Enable RMII clock output for VSC8541 PHY (2026-02-11 09:41:26
+0100)
----------------------------------------------------------------
AMD/Xilinx/FPGA changes for v2026.04-rc3
clk:
- zynqmp clk fixes
phy:
- sync vsc8541 config
versal2:
- fix GIC configuration
----------------------------------------------------------------
Maheedhar Bollapalli (1):
arm64: versal2: fix GICD/GICR base addresses for Versal Gen 2
Peter Korsgaard (2):
drivers/clk/Kconfig: fix "related" typo in help text
drivers/clk/clk_zynqmp.c: get rid of compiler warning for !CONFIG_CMD_CLK
builds
Pranav Tilak (1):
net: phy: mscc: Enable RMII clock output for VSC8541 PHY
drivers/clk/Kconfig | 4 ++--
drivers/clk/clk_zynqmp.c | 2 ++
drivers/net/phy/mscc.c | 2 +-
include/configs/amd_versal2.h | 4 ++--
4 files changed, 7 insertions(+), 5 deletions(-)
