On Wed, Mar 11, 2026 at 03:20:43PM +0100, Luca Weiss wrote: > Import the configuration for the Milos SoC from Linux.
Please update commit message to reflect the Linux commit/tag from where the configuration is imported. With that feel free to add: Reviewed-by: Sumit Garg <[email protected]> -Sumit > > Signed-off-by: Luca Weiss <[email protected]> > --- > drivers/phy/qcom/phy-qcom-qmp-ufs.c | 88 > +++++++++++++++++++++++++++++++++++++ > 1 file changed, 88 insertions(+) > > diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c > b/drivers/phy/qcom/phy-qcom-qmp-ufs.c > index 907f34744eb..80eba734a63 100644 > --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c > @@ -119,6 +119,68 @@ static const unsigned int > ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { > [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, > }; > > +static const struct qmp_ufs_init_tbl milos_ufsphy_serdes[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f), > +}; > + > +static const struct qmp_ufs_init_tbl milos_ufsphy_tx[] = { > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0xcc), > +}; > + > +static const struct qmp_ufs_init_tbl milos_ufsphy_rx[] = { > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94), > +}; > + > +static const struct qmp_ufs_init_tbl milos_ufsphy_pcs[] = { > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), > +}; > + > static const struct qmp_ufs_init_tbl sdm845_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), > QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), > @@ -982,6 +1044,31 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 > = { > .rx2 = 0x1a00, > }; > > +static const struct qmp_ufs_cfg milos_ufsphy_cfg = { > + .lanes = 2, > + > + .offsets = &qmp_ufs_offsets_v6, > + > + .tbls = { > + .serdes = milos_ufsphy_serdes, > + .serdes_num = ARRAY_SIZE(milos_ufsphy_serdes), > + .tx = milos_ufsphy_tx, > + .tx_num = ARRAY_SIZE(milos_ufsphy_tx), > + .rx = milos_ufsphy_rx, > + .rx_num = ARRAY_SIZE(milos_ufsphy_rx), > + .pcs = milos_ufsphy_pcs, > + .pcs_num = ARRAY_SIZE(milos_ufsphy_pcs), > + }, > + .tbls_hs_b = { > + .serdes = sm8550_ufsphy_hs_b_serdes, > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), > + }, > + > + .vreg_list = qmp_ufs_vreg_l, > + .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l), > + .regs = ufsphy_v6_regs_layout, > +}; > + > static const struct qmp_ufs_cfg sdm845_ufsphy_cfg = { > .lanes = 2, > > @@ -1651,6 +1738,7 @@ static struct phy_ops qmp_ufs_ops = { > }; > > static const struct udevice_id qmp_ufs_ids[] = { > + { .compatible = "qcom,milos-qmp-ufs-phy", .data = > (ulong)&milos_ufsphy_cfg, }, > { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = > (ulong)&sa8775p_ufsphy_cfg, }, > { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = > (ulong)&sdm845_ufsphy_cfg }, > { .compatible = "qcom,sm6350-qmp-ufs-phy", .data = > (ulong)&sdm845_ufsphy_cfg }, > > -- > 2.53.0 >
