[RFC PATCH 09/19] board: ti: j784s4: Add exit retention for k3-ddrss (J784s4)

[Prasanth Babu Mantena]

From: Richard Genoud <richard.gen...@bootlin.com>

Add the board specific part of the exit retention sequence for k3-ddrss
Following the DDR resume sequence,
   - exit DDR from retention
   - de-assert the DDR_RET pin
   - restore DDR max frequency
   - exit DDR from low power

Signed-off-by: Richard Genoud <richard.gen...@bootlin.com>
Signed-off-by: Prasanth Babu Mantena <p-mant...@ti.com>
---
 arch/arm/mach-k3/j784s4/j784s4_init.c | 53 +++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm/mach-k3/j784s4/j784s4_init.c 
b/arch/arm/mach-k3/j784s4/j784s4_init.c
index 161c68e474f..f039eb3f752 100644
--- a/arch/arm/mach-k3/j784s4/j784s4_init.c
+++ b/arch/arm/mach-k3/j784s4/j784s4_init.c
@@ -18,6 +18,8 @@
 #include <mmc.h>
 #include <remoteproc.h>
 #include <k3_bist.h>
+#include <power/pmic.h>
+#include <mach/k3-ddr.h>
 
 #include "../sysfw-loader.h"
 #include "../common.h"
@@ -264,15 +266,44 @@ void k3_spl_init(void)
                k3_dm_print_ver();
 }
 
+#define DDR_RET_VAL BIT(5)
+#define GPIO_OUT_1 0x3D
+#define PMIC_NSLEEP_REG 0x86
+
+static void k3_deassert_DDR_RET(void)
+{
+       struct udevice *pmic;
+       int regval;
+       int err;
+
+       err = uclass_get_device_by_name(UCLASS_PMIC,
+                                       "pmic@48", &pmic);
+       if (err) {
+               printf("Getting PMIC init failed: %d\n", err);
+               return;
+       }
+
+       /* Set DDR_RET Signal Low on PMIC B */
+       regval = pmic_reg_read(pmic, GPIO_OUT_1) & ~DDR_RET_VAL;
+
+       pmic_reg_write(pmic, GPIO_OUT_1, regval);
+       pmic_reg_write(pmic, PMIC_NSLEEP_REG, 0x3);
+}
+
 void k3_mem_init(void)
 {
        struct udevice *dev;
        int ret, ctrl = 0;
 
        if (IS_ENABLED(CONFIG_K3_J721E_DDRSS)) {
+               struct udevice *devs[J784S4_MAX_DDR_CONTROLLERS];
+               struct k3_ddrss_regs regs[J784S4_MAX_DDR_CONTROLLERS];
+
                ret = uclass_get_device(UCLASS_RAM, 0, &dev);
                if (ret)
                        panic("DRAM 0 init failed: %d\n", ret);
+
+               devs[0] = dev;
                ctrl++;
 
                while (ctrl < J784S4_MAX_DDR_CONTROLLERS) {
@@ -282,8 +313,30 @@ void k3_mem_init(void)
 
                        if (ret)
                                panic("DRAM %d init failed: %d\n", ctrl, ret);
+                       devs[ctrl] = dev;
                        ctrl++;
                }
+
+               if (board_is_resuming()) {
+                       /* exit DDRs from retention */
+                       for (ctrl = 0; ctrl < J784S4_MAX_DDR_CONTROLLERS; 
ctrl++) {
+                               k3_ddrss_lpddr4_exit_retention(devs[ctrl],
+                                                              &regs[ctrl]);
+                       }
+
+                       /* de-assert DDR_RET pin */
+                       k3_deassert_DDR_RET();
+
+                       /* restore DDR max frequency */
+                       for (ctrl = 0; ctrl < J784S4_MAX_DDR_CONTROLLERS; 
ctrl++)
+                               k3_ddrss_lpddr4_change_freq(devs[ctrl]);
+
+                       /* exit DDR from low power */
+                       for (ctrl = 0; ctrl < J784S4_MAX_DDR_CONTROLLERS; 
ctrl++) {
+                               k3_ddrss_lpddr4_exit_low_power(devs[ctrl],
+                                                              &regs[ctrl]);
+                       }
+               }
                printf("Initialized %d DRAM controllers\n", ctrl);
        }
 
-- 
2.34.1