Hi David, Le 19/07/2011 09:44, David Jander a écrit : > > Hi Stefano, > > On Mon, 18 Jul 2011 18:55:05 +0200 > Stefano Babic<[email protected]> wrote: > >> On 07/18/2011 05:18 PM, David Jander wrote: >>> >>> Hi all, >> >> Hi David, >> >>> What is going on here? Why did this work with caches enabled before?? >> >> I think cache was always disabled.. > > I had even L2-caches enabled in u-boot (copied/adapted some code from OMAP > cache.S), and called i/dcache_enable() from board code like this: > > int board_late_init(void) > { > power_init(); > probe_board_type(); > icache_enable(); > dcache_enable(); > > return 0; > } > > Is there a reason this wouldn't have worked before? > > Suppose it didn't. Does that mean we need to use the MMU to properly mark > regions of register space and specially FEC BD's as not-cached? Or do we need > to flash caches manually each time such a memory region is accessed? > I am kind of a CPU-speed-junkie, so I am not sure I want to live without > caches enabled in u-boot ;-)
You would have to flush (before sending packets / starting external memory-to-device DMA) and invalidate (before reading received packets / after external device-to-memory DMA is done); using MMU and mapping cached/non-cached areas is IMO overkill, and will hurt CPU accesses to the xmit/receive buffers and descriptors. > Best regards, Amicalement, -- Albert. _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
