On 3/29/26 7:49 AM, Kumar, Udit wrote:
[...]
+config CPU_V8M
+ bool
+ select CPU_V78M
+ select SYS_CACHE_SHIFT_6
referring to M55 TRM [0], (which seems to be next processor in this
family) page- (68-69) CCSIDR,
LTM cache size is not default to 64.
my suggestion will be to keep cache line same as of V7M, unless you
think otherwise.
You're right, I did switch the shift to 5 for both V7M and V8M in v2.
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -4,6 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, [email protected].
extra-y := start.o
-obj-y += cpu.o cache.o
+obj-y += cache.o
+obj-$(CONFIG_CPU_V7M) += cpu.o
Why you are dropping cpu.c compilation
Mainly because its content was not useful, but I isolated the content a
bit better in V2. The only thing which is not applicable to V8M is the
AIRCR reset, which is no longer present on CM33. The rest can be gated
by other Kconfig symbols.
