On 5/5/26 8:54 AM, Chee, Tien Fong wrote:
Hi Alif,
On 28/4/2026 11:32 am, [email protected] wrote:
From: Alif Zakuan Yuslaimi <[email protected]>
The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case.
This implementation turns the caches on temporarily, then overwrites the
whole RAM with zeroes, flushes the caches and turns them off again.
This provides satisfactory performance.
Move common code sdram_init_ecc_bits() to new common file sdram_soc32.c.
Preparation for Gen5 uses the same memory initialization function as
Arria10.
New Kconfig is introduced to enable this implementation only on the
default
Arria10 and CycloneV boards as this will increase the SPL size which
will exceed some Gen5 devices' SPL size limit.
The subject is severely misleading, the ECC scrubbing was upstream since
2018:
07252f6f7e37 ("ddr: altera: Add ECC DRAM scrubbing support for Arria10")
ddr: altera: Add ECC DRAM scrubbing support for Arria10
The SDRAM must first be rewritten by zeroes if ECC is used to
initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case. This scrubbing implementation turns the caches on
temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns them
off again. This provides satisfactory performance.
Even the commit message of this patch is a duplicate of that one in the
commit from 2018 ? What is going on here ?
