The K1 build now consumes the kernel device tree via OF_UPSTREAM. The local copies under arch/riscv/dts/ (k1.dtsi, k1-pinctrl.dtsi, k1-bananapi-f3.dts) are unreachable; remove them.
Signed-off-by: Guodong Xu <[email protected]> --- arch/riscv/dts/k1-bananapi-f3.dts | 28 --- arch/riscv/dts/k1-pinctrl.dtsi | 19 -- arch/riscv/dts/k1.dtsi | 480 -------------------------------------- 3 files changed, 527 deletions(-) diff --git a/arch/riscv/dts/k1-bananapi-f3.dts b/arch/riscv/dts/k1-bananapi-f3.dts deleted file mode 100644 index 6b5b83bcdb9..00000000000 --- a/arch/riscv/dts/k1-bananapi-f3.dts +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2024 Yangyu Chen <[email protected]> - */ - -#include "k1.dtsi" -#include "binman.dtsi" -#include "k1-pinctrl.dtsi" - -/ { - model = "Banana Pi BPI-F3"; - compatible = "bananapi,bpi-f3", "spacemit,k1"; - - chosen { - stdout-path = "serial0"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x00000000 0x00000000 0x80000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_2_cfg>; - status = "okay"; -}; diff --git a/arch/riscv/dts/k1-pinctrl.dtsi b/arch/riscv/dts/k1-pinctrl.dtsi deleted file mode 100644 index 14e7096fbcf..00000000000 --- a/arch/riscv/dts/k1-pinctrl.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 Spacemit Inc. - * Copyright (C) 2025 Yixun Lan <[email protected]> - */ - -#define K1_PADCONF(pin, func) (((pin) << 16) | (func)) - -&pinctrl { - uart0_2_cfg: uart0-2-cfg { - uart0-2-pins { - pinmux = <K1_PADCONF(68, 2)>, - <K1_PADCONF(69, 2)>; - - bias-pull-up = <0>; - drive-strength = <32>; - }; - }; -}; diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi deleted file mode 100644 index a633e43da32..00000000000 --- a/arch/riscv/dts/k1.dtsi +++ /dev/null @@ -1,480 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -/* - * Copyright (C) 2024 Yangyu Chen <[email protected]> - */ - -/dts-v1/; -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "SpacemiT K1"; - compatible = "spacemit,k1"; - - aliases { - serial0 = &uart0; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &uart6; - serial6 = &uart7; - serial7 = &uart8; - serial8 = &uart9; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <24000000>; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu_0>; - }; - core1 { - cpu = <&cpu_1>; - }; - core2 { - cpu = <&cpu_2>; - }; - core3 { - cpu = <&cpu_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&cpu_4>; - }; - core1 { - cpu = <&cpu_5>; - }; - core2 { - cpu = <&cpu_6>; - }; - core3 { - cpu = <&cpu_7>; - }; - }; - }; - - cpu_0: cpu@0 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <0>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_1: cpu@1 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <1>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu1_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_2: cpu@2 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <2>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu2_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_3: cpu@3 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <3>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster0_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu3_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_4: cpu@4 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <4>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu4_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_5: cpu@5 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <5>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu5_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_6: cpu@6 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <6>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu6_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cpu_7: cpu@7 { - compatible = "spacemit,x60", "riscv"; - device_type = "cpu"; - reg = <7>; - riscv,isa = "rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_svinval_svnapot_svpbmt"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicbom", - "zicbop", "zicboz", "zicntr", "zicond", "zicsr", - "zifencei", "zihintpause", "zihpm", "zfh", "zba", - "zbb", "zbc", "zbs", "zkt", "zvfh", "zvkt", - "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt"; - riscv,cbom-block-size = <64>; - riscv,cbop-block-size = <64>; - riscv,cboz-block-size = <64>; - i-cache-block-size = <64>; - i-cache-size = <32768>; - i-cache-sets = <128>; - d-cache-block-size = <64>; - d-cache-size = <32768>; - d-cache-sets = <128>; - next-level-cache = <&cluster1_l2_cache>; - mmu-type = "riscv,sv39"; - - cpu7_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - cluster0_l2_cache: l2-cache0 { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <512>; - cache-unified; - }; - - cluster1_l2_cache: l2-cache1 { - compatible = "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-size = <524288>; - cache-sets = <512>; - cache-unified; - }; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <2>; - #size-cells = <2>; - dma-noncoherent; - ranges; - - uart0: serial@d4017000 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017000 0x0 0x100>; - interrupts = <42>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@d4017100 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017100 0x0 0x100>; - interrupts = <44>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@d4017200 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017200 0x0 0x100>; - interrupts = <45>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@d4017300 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017300 0x0 0x100>; - interrupts = <46>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart5: serial@d4017400 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017400 0x0 0x100>; - interrupts = <47>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart6: serial@d4017500 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017500 0x0 0x100>; - interrupts = <48>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart7: serial@d4017600 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017600 0x0 0x100>; - interrupts = <49>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart8: serial@d4017700 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017700 0x0 0x100>; - interrupts = <50>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart9: serial@d4017800 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xd4017800 0x0 0x100>; - interrupts = <51>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - plic: interrupt-controller@e0000000 { - compatible = "spacemit,k1-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xe0000000 0x0 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>, - <&cpu5_intc 11>, <&cpu5_intc 9>, - <&cpu6_intc 11>, <&cpu6_intc 9>, - <&cpu7_intc 11>, <&cpu7_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - riscv,ndev = <159>; - }; - - clint: timer@e4000000 { - compatible = "spacemit,k1-clint", "sifive,clint0"; - reg = <0x0 0xe4000000 0x0 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, - <&cpu1_intc 3>, <&cpu1_intc 7>, - <&cpu2_intc 3>, <&cpu2_intc 7>, - <&cpu3_intc 3>, <&cpu3_intc 7>, - <&cpu4_intc 3>, <&cpu4_intc 7>, - <&cpu5_intc 3>, <&cpu5_intc 7>, - <&cpu6_intc 3>, <&cpu6_intc 7>, - <&cpu7_intc 3>, <&cpu7_intc 7>; - }; - - sec_uart1: serial@f0612000 { - compatible = "spacemit,k1-uart", "intel,xscale-uart"; - reg = <0x0 0xf0612000 0x0 0x100>; - interrupts = <43>; - clock-frequency = <14857000>; - reg-shift = <2>; - reg-io-width = <4>; - status = "reserved"; /* for TEE usage */ - }; - - reset: reset-controller@d4050000 { - compatible = "spacemit,k1-reset"; - reg = <0x0 0xd4050000 0x0 0x209c>, - <0x0 0xd4282800 0x0 0x400>, - <0x0 0xd4015000 0x0 0x1000>, - <0x0 0xd4090000 0x0 0x1000>, - <0x0 0xd4282c00 0x0 0x400>, - <0x0 0xd8440000 0x0 0x98>, - <0x0 0xc0000000 0x0 0x4280>, - <0x0 0xf0610000 0x0 0x20>; - reg-names = "mpmu", "apmu", "apbc", "apbs", "ciu", "dciu", "ddrc", "apbc2"; - #reset-cells = <1>; - status = "disabled"; - }; - - pinctrl: pinctrl@d401e000 { - compatible = "spacemit,k1-pinctrl", "pinctrl-single"; - reg = <0x0 0xd401e000 0x0 0x400>; - pinctrl-single,register-width = <32>; - }; - }; -}; -- 2.43.0
