On Tue May 12, 2026 at 4:33 PM IST, Anshul Dalal wrote:
> Currently the sequence to enable caches for the A53/A72 core on K3
> devices looks as follows:
>
> 1. Map entire DDR banks
> 2. Setup page tables and enable MMU (done by mmu_setup)
> 3. Unmap reserved-memory regions
> 4. Enable caches
>
> However there is a brief period of execution between #2 and #3 where the
> core can issue speculative accesses to the entire DDR space (including
> the reserved-memory regions) despite the caches being disabled.
>
> A firewall exception is triggered whenever such speculative access is
> made to secure DDR region of TFA or OP-TEE. This patch fixes the issue
> by re-ordering the sequence as follows:
>
> 1. Map entire DDR banks
> 2. Setup page tables
> 3. Unmap reserved-memory regions
> 4. Enable MMU
> 5. Enable caches
>
> Fixes: f1c694b8fdde ("mach-k3: map all banks using mem_map_from_dram_banks")
> Signed-off-by: Anshul Dalal <[email protected]>
Forgot to add:
Reported-by: Suhaas Joshi <[email protected]>
--
Anshul Dalal <[email protected]>
