Hi Daniele,
On 5/18/2026 11:04 PM, Daniele Briguglio wrote:
> The Rock 5 ITX uses a PI6C 100MHz oscillator to drive its M.2 M-key
> and SATA PCIe3 controllers. In the Linux DTS the oscillator is
> described as a "gated-fixed-clock" node and added to the clocks
> list of pcie3x4 and pcie3x2 so that either controller's probe
> enables the supply.
>
> U-Boot has no driver for the gated-fixed-clock compatible, so
> clk_get_bulk() in pcie_dw_rockchip fails with -ENODEV on the
> phandle and the PCIe3 controllers never come up:
>
> pcie_dw_rockchip pcie@fe150000: Can't get clock: -19
> pcie_dw_rockchip pcie@fe160000: Can't get clock: -19
>
> Override the clocks/clock-names of pcie3x4 and pcie3x2 in the
> u-boot dtsi to keep only the CRU clocks. vcc3v3_mkey is already
> regulator-always-on here and is the same regulator node as
> vcc3v3_pi6c_05, so the oscillator stays powered and the "ref"
> input ticks regardless. The Linux DTB is unchanged.
Linux and other OSs can be and are affected by U-Boot changes to the DT,
especially when UEFI is used to boot or when no external DT is supplied
while booting.
Please instead look into adding a simple UCLASS_CLK driver for the
gated-fixed-clock compatible, it should likely be a very simple driver.
clock-frequency prop value should be returned from .get_rate() clk ops
the vdd-supply regulator should be enabled in the .enable() clk ops, and
possible also request the enable-gpios pin to be active.
Following could possible be something for you to build upon (untested):
struct gated_fixed_clock_priv {
struct udevice *supply;
};
int gated_fixed_clock_enable(struct clk *clk)
{
struct gated_fixed_clock_priv *priv = dev_get_priv(clk->dev);
return regulator_set_enable_if_allowed(priv->supply, true);
}
int gated_fixed_clock_disable(struct clk *clk)
{
struct gated_fixed_clock_priv *priv = dev_get_priv(clk->dev);
return regulator_set_enable_if_allowed(priv->supply, false);
}
static int gated_fixed_clock_probe(struct udevice *dev)
{
struct gated_fixed_clock_priv *priv = dev_get_priv(dev);
return device_get_supply_regulator(dev, "vdd-supply", &priv->supply);
}
static struct clk_ops gated_fixed_clock_ops = {
.enable = gated_fixed_clock_enable,
.disable = gated_fixed_clock_disable,
};
static const struct udevice_id gated_fixed_clock_ids[] = {
{ .compatible = "gated-fixed-clock" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(gated_fixed_clock) = {
.name = "gated_fixed_clock",
.id = UCLASS_CLK,
.of_match = gated_fixed_clock_ids,
.probe = gated_fixed_clock_probe,
.priv_auto = sizeof(struct gated_fixed_clock_priv),
.ops = &gated_fixed_clock_ops,
};
Regards,
Jonas
>
> Link: https://lore.kernel.org/r/[email protected]
> Signed-off-by: Daniele Briguglio <[email protected]>
> ---
> Tested on a Rock 5 ITX with an NVMe drive in the M.2 M-key slot.
> ---
> arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi
> b/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi
> index 1e5c2674e..51ca79653 100644
> --- a/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588-rock-5-itx-u-boot.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include "rk3588-u-boot.dtsi"
> +#include <dt-bindings/clock/rockchip,rk3588-cru.h>
>
> &fspim2_pins {
> bootph-pre-ram;
> @@ -20,3 +21,22 @@
> &vcc3v3_mkey {
> regulator-always-on;
> };
> +
> +/* Drop pcie30_port{0,1}_refclk: U-Boot has no gated-fixed-clock driver. */
> +&pcie3x4 {
> + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk",
> + "aux", "pipe";
> +};
> +
> +&pcie3x2 {
> + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
> + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
> + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk",
> + "aux", "pipe";
> +};
>
> ---
> base-commit: 38dbe637c9dfcadbd1bc201bfbb27f96b2ad525a
> change-id: 20260518-rock-5-itx-pcie-refclk-dtsi-17ad4b21df1d
>
> Best regards,
> --
> Daniele Briguglio <[email protected]>
>
