Brian pointed out that SPL can support VIDEO, PANEL, and SPLASH_SCREEN,
so guarding select_ldb_di_clock_source() with !CONFIG_SPL_BUILD was too
broad — it excluded SPL builds that legitimately need the LDB clocks.
- b1x5v2: guard with CONFIG_SPL_VIDEO as Brian suggested
- aristainetos: guard with CONFIG_VIDEO_IPUV3 (no SPL on this board)
- clk-imx6q: fix guard mismatch — imx6q_init_ldb_clks() was defined
only for CONFIG_SPL_VIDEO but called for !CONFIG_SPL_BUILD, causing
a build failure on non-SPL boards using CONFIG_VIDEO_IPUV3; use
(!CONFIG_SPL_BUILD || CONFIG_SPL_VIDEO) on both definition and call
Fixes: faa4793ad3d ("clk: imx6q: guard LDB clock init with CONFIG_SPL_BUILD")
Signed-off-by: Md Shofiqul Islam <[email protected]>
---
board/aristainetos/aristainetos.c | 2 ++
board/ge/b1x5v2/b1x5v2.c | 3 ++-
drivers/clk/imx/clk-imx6q.c | 6 +++---
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/board/aristainetos/aristainetos.c
b/board/aristainetos/aristainetos.c
index 4a2349e165b..c163b49209e 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -218,7 +218,9 @@ static void set_gpr_register(void)
int board_early_init_f(void)
{
+#if defined(CONFIG_VIDEO_IPUV3)
select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
+#endif
set_gpr_register();
/*
diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c
index f7751fd6fb1..da7cb880eeb 100644
--- a/board/ge/b1x5v2/b1x5v2.c
+++ b/board/ge/b1x5v2/b1x5v2.c
@@ -320,8 +320,9 @@ int overwrite_console(void)
int board_early_init_f(void)
{
+#if defined(CONFIG_SPL_VIDEO)
select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK);
-
+#endif
return 0;
}
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 379155096e8..5be303468a9 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -156,7 +156,7 @@ static struct clk_div_table video_div_table[] = {
static unsigned int share_count_mipi_core_cfg;
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_VIDEO)
static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel,
int *ldb_di1_sel)
{
@@ -271,7 +271,7 @@ static void imx6q_init_ldb_clks(struct udevice *dev)
select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]);
}
-#endif /* !CONFIG_SPL_BUILD */
+#endif /* !CONFIG_SPL_BUILD || CONFIG_SPL_VIDEO */
static int imx6q_clk_probe(struct udevice *dev)
{
@@ -490,7 +490,7 @@ static int imx6q_clk_probe(struct udevice *dev)
* Need to set the clocks now and make them read-only due to a
* hardware bug. Fixed on the i.MX6 QuadPlus
*/
-#if !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_VIDEO)
imx6q_init_ldb_clks(dev);
#endif
clk_dm(IMX6QDL_CLK_LDB_DI0_SEL,
--
2.51.1
