From: Raymond Mao <[email protected]> Make the K1 clock controllers visible to SPL by tagging the four root fixed clocks (osc_32k, vctcxo_{1,3,24}m) and the four syscon nodes (mpmu, pll, apmu, apbc) with bootph-pre-ram in the BPI-F3 U-Boot overlay.
Signed-off-by: Raymond Mao <[email protected]> Signed-off-by: Guodong Xu <[email protected]> --- v4: - Drop v3's separate k1-spl.dts (which #included k1.dtsi from the local fork); place SPL bootph-pre-ram markers in k1-bananapi-f3-u-boot.dtsi against the upstream-mirrored BPI-F3 DT. - Extend APBC clocks/clock-names with pll1_d78_31p5 (MPMU) and pll1_d4 (PLL controller). The kernel registers these via clk_register_fixed_factor at runtime; U-Boot's CCF resolves them through DT, so they must be listed for probe ordering. --- arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi | 32 +++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi index 4e4d0e0c49e..fbee8763a21 100644 --- a/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi +++ b/arch/riscv/dts/k1-bananapi-f3-u-boot.dtsi @@ -32,3 +32,35 @@ &uart0 { bootph-pre-ram; }; + +&osc_32k { + bootph-pre-ram; +}; + +&vctcxo_1m { + bootph-pre-ram; +}; + +&vctcxo_3m { + bootph-pre-ram; +}; + +&vctcxo_24m { + bootph-pre-ram; +}; + +&syscon_mpmu { + bootph-pre-ram; +}; + +&pll { + bootph-pre-ram; +}; + +&syscon_apmu { + bootph-pre-ram; +}; + +&syscon_apbc { + bootph-pre-ram; +}; -- 2.43.0
