On Mon, 18 May 2026 at 14:54, Anshul Dalal <[email protected]> wrote: > > Currently the sequence to enable caches for the A53/A72 core on K3 > devices looks as follows: > > 1. Map entire DDR banks > 2. Setup page tables (done by mmu_setup) > 3. Enable MMU > 4. Unmap reserved-memory regions > 5. Enable caches > > However there is a brief period of execution between #3 and #4 where the > core can issue speculative accesses to the entire DDR space (including > the reserved-memory regions) despite the caches being disabled. > > A firewall exception is triggered whenever such speculative access is > made to secure DDR region of TFA or OP-TEE. This patch fixes the issue > by re-ordering the sequence as follows: > > 1. Map entire DDR banks > 2. Setup page tables > 3. Unmap reserved-memory regions > 4. Enable MMU > 5. Enable caches > > Fixes: f1c694b8fdde ("mach-k3: map all banks using mem_map_from_dram_banks") > Reported-by: Suhaas Joshi <[email protected]> > Signed-off-by: Anshul Dalal <[email protected]> > --- > arch/arm/mach-k3/common.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c > index 396018b7a7a..9bebc0b1106 100644 > --- a/arch/arm/mach-k3/common.c > +++ b/arch/arm/mach-k3/common.c > @@ -295,6 +295,7 @@ void enable_caches(void) > __func__, ret); > } > > + mmu_enable();
You added mm_enable() on the previous patch a few lines above. I assumed it was to keep the code changes confined to one patch without changing the behavior, but you have to remove it now. You can even skip it entirely since dcache_enable() will do it, but I don't mind having the explicit call. Cheers /Ilias > icache_enable(); > dcache_enable(); > } > > -- > 2.53.0 >
