From: Tanmay Kathpalia <[email protected]> Add dedicated device tree and configuration support for Agilex5 Modular DevKit which uses an external GPIO expander for 1.8V signaling control instead of the onboard GPIO used in the Premium DevKit variant.
New files added: - socfpga_agilex5_socdk_modular.dts: Main device tree for modular board - socfpga_agilex5_socdk_modular-u-boot.dtsi: U-Boot specific additions - configs/socfpga_agilex5_modular_defconfig: Modular board configuration Key differences from Premium DevKit: - Uses PCA9535 GPIO expander (I2C address 0x27) for voltage switching - GPIO expander pin 1 controls the level shifter for SD I/O voltage - Requires I2C3 and PCA953X driver support in SPL and main U-Boot - Same SD timing configurations but different GPIO control mechanism Configuration changes: - Enable CONFIG_SPL_I2C and CONFIG_SPL_SYS_I2C_DW for SPL I2C support - Enable CONFIG_DM_PCA953X and CONFIG_SPL_DM_PCA953X for GPIO expander - Enable CONFIG_DM_REGULATOR_GPIO and CONFIG_SPL_DM_REGULATOR_GPIO - Add TARGET_SOCFPGA_AGILEX5_MODULAR Kconfig option Hardware features: - SD card support with UHS-I timing configurations - NAND disabled in favor of MMC boot priority - Same memory configuration options as Premium DevKit Signed-off-by: Tanmay Kathpalia <[email protected]> Signed-off-by: Tze Yee Ng <[email protected]> Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> --- .../socfpga_agilex5_socdk_modular-u-boot.dtsi | 157 ++++++++++++++++++ .../arm/dts/socfpga_agilex5_socdk_modular.dts | 75 +++++++++ configs/socfpga_agilex5_modular_defconfig | 9 + 3 files changed, 241 insertions(+) create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_modular-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex5_socdk_modular.dts create mode 100644 configs/socfpga_agilex5_modular_defconfig diff --git a/arch/arm/dts/socfpga_agilex5_socdk_modular-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk_modular-u-boot.dtsi new file mode 100644 index 00000000000..a91624864c4 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk_modular-u-boot.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions for Agilex5 SoCDK Modular + * + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include "socfpga_agilex5-u-boot.dtsi" + +/{ + aliases { + spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@0x20000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0x20000450 0x00000010>; + status = "disabled"; + }; + }; + + /* + * Both Memory base address and size default info is retrieved from HW setting. + * Reconfiguration / Overwrite these info can be done with examples below. + * + * When LPDDR ECC is enabled, the last 1/8 of the memory region must + * be reserved for the Inline ECC buffer. + * + * Example for memory size with 2GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>; + * }; + * + * Example for memory size with 8GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x80000000>; + * }; + * + * Example for memory size with 32GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>; + * }; + * + * Example for memory size with 512GB: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x7 0x80000000>, + * <0x88 0x00000000 0x78 0x00000000>; + * }; + * + * Example for memory size with 2GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x70000000>; + * }; + * + * Example for memory size with 8GB with LPDDR Inline ECC ON: + * memory { + * reg = <0x0 0x80000000 0x0 0x80000000>, + * <0x8 0x80000000 0x1 0x40000000>; + * }; + */ + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &mmc,&flash0,"/memory"; + }; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + bootph-all; + /delete-property/ cdns,read-delay; +}; + +&flash1 { + bootph-all; +}; + +&i3c0 { + status = "disabled"; +}; + +&i3c1 { + status = "disabled"; +}; + +&qspi { + status = "okay"; +}; + +&nand { + status = "disabled"; +}; + +&timer0 { + bootph-all; +}; + +&timer1 { + bootph-all; +}; + +&timer2 { + bootph-all; +}; + +&timer3 { + bootph-all; +}; + +&gmac0 { + status = "okay"; + /* PHY delays is configured via skew properties */ + phy-mode = "rgmii"; + phy-handle = <&emac0_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac0_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac2 { + status = "okay"; + /* PHY delays is configured via skew properties */ + phy-mode = "rgmii"; + phy-handle = <&emac2_phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwxgmac-mdio"; + emac2_phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +#if !defined(CONFIG_SOCFPGA_SECURE_VAB_AUTH) +&binman { + /delete-node/ kernel; +}; +#endif diff --git a/arch/arm/dts/socfpga_agilex5_socdk_modular.dts b/arch/arm/dts/socfpga_agilex5_socdk_modular.dts new file mode 100644 index 00000000000..367948bcbc2 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex5_socdk_modular.dts @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 Altera Corporation <www.altera.com> + */ + +#include "socfpga_agilex5_socdk.dts" + +&i2c3 { + bootph-all; + status = "okay"; + + expander1: gpio@27 { + compatible = "nxp,pca9535"; + reg = <0x27>; /* SoM expander address */ + gpio-controller; + #gpio-cells = <2>; + bootph-all; + }; +}; + +&sd_emmc_power { + bootph-all; +}; + +&sd_io_1v8_reg { + gpios = <&expander1 1 GPIO_ACTIVE_HIGH>; + bootph-all; +}; + +&mmc { + status = "okay"; + + no-mmc; + disable-wp; + cap-sd-highspeed; + vmmc-supply = <&sd_emmc_power>; + vqmmc-supply = <&sd_io_1v8_reg>; + max-frequency = <200000000>; + sdhci-caps = <0x00000000 0x0000c800>; + + /* SD card default speed (DS) and UHS-I SDR12 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-ds = <0x00780000>; + cdns,phy-gate-lpbk-ctrl-delay-sd-ds = <0x81a40040>; + cdns,phy-dll-slave-ctrl-sd-ds = <0x00a000fe>; + cdns,phy-dq-timing-delay-sd-ds = <0x28000001>; + + /* SD card high speed and UHS-I SDR25 mode timing configuration */ + cdns,phy-dqs-timing-delay-sd-hs = <0x780001>; + cdns,phy-gate-lpbk-ctrl-delay-sd-hs = <0x81a40040>; + cdns,phy-dq-timing-delay-sd-hs = <0x10000001>; + cdns,ctrl-hrs16-slave-ctrl-sd-hs = <0x101>; + cdns,ctrl-hrs07-timing-delay-sd-hs = <0xA0001>; + + /* SD card UHS-I SDR50 mode timing configuration */ + cdns,phy-dqs-timing-delay-emmc-sdr = <0x780004>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-sdr = <0x80a40040>; + cdns,phy-dll-slave-ctrl-emmc-sdr = <0x4000004>; + cdns,phy-dq-timing-delay-emmc-sdr = <0x38000001>; + cdns,ctrl-hrs09-timing-delay-emmc-sdr = <0xf1c1800c>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-sdr = <0x20000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-sdr = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-sdr = <0x90005>; + + /* SD card UHS-I SDR104 mode timing configuration */ + cdns,phy-dq-timing-delay-emmc-hs200 = <0x11000001>; + cdns,phy-dqs-timing-delay-emmc-hs200 = <0x780004>; + cdns,phy-dll-slave-ctrl-emmc-hs200 = <0x4d4d00>; + cdns,phy-gate-lpbk-ctrl-delay-emmc-hs200 = <0x81a40040>; + cdns,ctrl-hrs09-timing-delay-emmc-hs200 = <0xf1c18000>; + cdns,ctrl-hrs10-lpbk-ctrl-delay-emmc-hs200 = <0x90000>; + cdns,ctrl-hrs16-slave-ctrl-emmc-hs200 = <0x101>; + cdns,ctrl-hrs07-timing-delay-emmc-hs200 = <0xa0001>; + + bootph-all; +}; diff --git a/configs/socfpga_agilex5_modular_defconfig b/configs/socfpga_agilex5_modular_defconfig new file mode 100644 index 00000000000..3f3a47f02ab --- /dev/null +++ b/configs/socfpga_agilex5_modular_defconfig @@ -0,0 +1,9 @@ +#include <configs/socfpga_agilex5_defconfig> + +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk_modular" +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_SYS_I2C_DW=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_PCA953X=y -- 2.43.7 base-commit: 29c3448791d3fbd8dd13a6e3b58547206a98d381 branch: master_agilex5_modular
