CONFIG_SPL_BUILD is only defined in SPL builds; TPL builds define CONFIG_XPL_BUILD (which covers both SPL and TPL) but not CONFIG_SPL_BUILD. The existing guards therefore do not exclude heavyweight clock functions (VOP, GMAC, UART frac) from TPL builds, inflating TPL size unnecessarily.
Replace all six CONFIG_SPL_BUILD guards with CONFIG_XPL_BUILD. This matches the pattern used in clk_px30.c and clk_rk3288.c. Signed-off-by: Johan Axelsson <[email protected]> --- drivers/clk/rockchip/clk_rk3576.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index 8f99a440a3e..3d9a1df4f2f 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -67,14 +67,14 @@ static struct rockchip_pll_clock rk3576_pll_clks[] = { RK3576_MODE_CON0, 10, 15, 0, rk3576_24m_pll_rates), }; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD #ifndef BITS_WITH_WMASK #define BITS_WITH_WMASK(bits, msk, shift) \ ((bits) << (shift)) | ((msk) << ((shift) + 16)) #endif #endif -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD /* * * rational_best_approximation(31415, 10000, @@ -925,7 +925,7 @@ static ulong rk3576_mmc_set_clk(struct rk3576_clk_priv *priv, return rk3576_mmc_get_clk(priv, clk_id); } -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD static ulong rk3576_aclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id) { @@ -1998,7 +1998,7 @@ static ulong rk3576_clk_get_rate(struct clk *clk) case TCLK_WDT0: rate = OSC_HZ; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case ACLK_VOP_ROOT: case ACLK_VOP: case ACLK_VO0_ROOT: @@ -2177,7 +2177,7 @@ static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate) case CLK_REF_PCIE1_PHY: ret = 0; break; -#ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_XPL_BUILD case ACLK_VOP_ROOT: case ACLK_VOP: case ACLK_VO0_ROOT: @@ -2400,7 +2400,7 @@ static int rk3576_clk_probe(struct udevice *dev) priv->sync_kernel = false; -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_XPL_BUILD /* relase presetn_bigcore_biu/cru/grf */ writel(0x1c001c00, 0x26010010); /* set spll to normal mode */ -- 2.45.1.windows.1
