The protection scheme that GD25B256 and all other chips with the same ID
supported is not compatible with the spi-nor driver:
This driver supports BP{0,1,2} + TB,
while GD25B256 implements BP{0,1,2,3} + TBLink: https://download.gigadevice.com/Datasheet/DS-00327-GD25B256D-Rev1.7.pdf Signed-off-by: Weijie Gao <[email protected]> --- v4: new --- drivers/mtd/spi/spi-nor-ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index fcc546fb5ae..cbac5114672 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -149,7 +149,7 @@ const struct flash_info spi_nor_ids[] = { }, /* adding these 3V QSPI flash parts */ {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K | - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) }, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES)}, {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)}, {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K | -- 2.45.2
