On Thu, May 28, 2026 at 03:49:06PM +0200, Emanuele Ghidoli wrote: > From: Emanuele Ghidoli <[email protected]> > > The Receive FIFO Enable (RXFE) field in the LPUART FIFO register is > bit 3 on all supported architectures. The define has been wrong since > it was introduced: for non-i.MX8/i.MXRT it set bit 6, which on LS102xA > is read-only-as-zero, so the bug went unnoticed. > > NXP confirmed bit 3 is correct everywhere, so drop the ARCH-based > selection. > > Link: > https://github.com/nxp-imx/uboot-imx/commit/9498bcc514737269bb0ca436f775460741ab8199 > Link: > https://lore.kernel.org/u-boot/[email protected]/ > Fixes: 6209e14cb026 ("serial: lpuart: add 32-bit registers lpuart support") > Signed-off-by: Emanuele Ghidoli <[email protected]>
Reviewed-by: Francesco Dolcini <[email protected]>
