On 5/12/2026 3:15 PM, Kathpalia, Tanmay wrote:
Hi Tze,
On 5/6/2026 7:44 AM, Peng Fan wrote:
On Mon, May 04, 2026 at 07:36:03PM -0700, [email protected] wrote:
From: Tze Yee Ng <[email protected]>
The Cadence SD6HC (SDHCI spec v4.20+) controller uses a soft PHY whose
DLL delay characteristics vary with PVT (Process, Voltage, Temperature)
and board-level trace routing.
A static delay value programmed via device tree for SD High Speed
mode is
insufficient because the optimal sampling point varies per board, SD
card,
and operating conditions. Runtime calibration is required.
While the SD Physical Layer Specification does not mandate tuning for
SD HS mode (only for UHS-I SDR50/SDR104), the Cadence SD6HC PHY
requires runtime calibration of its receive data delay line to find a
valid sampling window under constrained clock conditions.
This characterization is incorrect. The SD Physical Layer Simplified
Specification v9.00 Section 4.2.4.5 explicitly states:
"CMD19 can be executed in transfer state of 1.8V signaling mode
while the card is unlocked. The other case, CMD19 is treated as
illegal command."
SD High Speed operates at 3.3V signaling. Issuing CMD19 in SD HS mode
would cause a spec-compliant SD card to return an ILLEGAL_COMMAND error.
The spec does not merely "not mandate" tuning for SD HS — it actively
forbids CMD19 outside of 1.8V signaling mode.
The tuning is triggered from the set_ios_post callback because at that
moment hardware has committed the new bus width, clock frequency,
and speed
mode to the controller registers. This ensuring the tuning sequence
runs
at the correct SD HS operating conditions.
The tuning is gated by a device tree property "cdns,sd-hs-tuning" so
that only boards requiring runtime calibration opt in. When enabled,
the driver performs a 40-tap DLL sweep using CMD19 to find the largest
consecutive passing window, then programs the midpoint into
PHY_DLL_SLAVE_CTRL_REG.
To enable on a board, add to the MMC node in device tree:
&mmc {
cdns,sd-hs-tuning;
Has this property been accepted by Linux Upstream?
Regards
Peng
};
Hi All,
I would like to revisit this change as I believe the earlier review concerns
raised by Peng and myself remain unresolved.
The patch enables tuning for SD High Speed (HS) mode. However:
* SD tuning is defined for UHS modes and is not part of the standard HS
mode operation.
* The Cadence SD6HC User Guide, Section 7.5.2 ("Tuning"), describes
tuning for SDR104 mode and does not indicate that tuning should be
performed in HS mode.
* The current implementation therefore appears inconsistent with both
the SD specification and the Cadence SD6HC documentation.
Since this patch modifies the SD6HC tuning flow, could someone clarify the
technical justification for performing tuning in HS mode?
Regards,
Tanmay
