On 9/6/2026 10:03 am, [email protected] wrote:
From: Alif Zakuan Yuslaimi <[email protected]>Share dram_bank_mmu_setup() between Gen5 and Arria10 in misc.c. Before relocation, map OCRAM and DRAM write-through so SPL can run sdram_init_ecc_bits() with dcache; after relocation, use default DRAM cache attributes. Fixes: 503eea451903 ("arm: cp15: update DACR value to activate access control") Link: e26ecebc684b ("socfpga: arria10: Allow dcache_enable before relocation") Signed-off-by: Alif Zakuan Yuslaimi <[email protected]> --- Changes in v4: - Commit message clean up Changes in v3: - Removed 'select SPL_CACHE if SPL' Kconfig guard from this patch and applied this condition alongside SOCFPGA_ECC_SUPPORT on patch 3 Changes in v2: - Shared dram_bank_mmu_setup() is set as optional via Kconfig and defaulted on only for the reference Arria10/CycloneV boards to avoid SPL overflows on size-limited Gen5 defconfigs. arch/arm/mach-socfpga/misc.c | 31 ++++++++++++++++++++++++++++ arch/arm/mach-socfpga/misc_arria10.c | 26 ----------------------- 2 files changed, 31 insertions(+), 26 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 1eef7893e54..80b054dcae9 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -318,3 +318,34 @@ phys_addr_t socfpga_get_clkmgr_addr(void) { return socfpga_clkmgr_base; } + +#if IS_ENABLED(CONFIG_SYS_ARM_CACHE_CP15) +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + u32 start, size; + int i; + + /* If we're still in OCRAM, don't set the XN bit on it */ + if (!(gd->flags & GD_FLG_RELOC)) { + set_section_dcache(CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, + DCACHE_WRITETHROUGH); + + /* + * The default implementation of this function allows the DRAM dcache + * to be enabled only after relocation. However, to speed up ECC + * initialization, we want to be able to enable DRAM dcache before + * relocation. + */ + start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + for (i = start; i < start + size; i++) + set_section_dcache(i, DCACHE_WRITETHROUGH); + } else { + start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; + for (i = start; i < start + size; i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); + } +} +#endif diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 7e0f3875b7c..635fc3568fb 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -243,29 +243,3 @@ int qspi_flash_software_reset(void) return 0; } #endif - -void dram_bank_mmu_setup(int bank) -{ - struct bd_info *bd = gd->bd; - u32 start, size; - int i; - - /* If we're still in OCRAM, don't set the XN bit on it */ - if (!(gd->flags & GD_FLG_RELOC)) { - set_section_dcache( - CFG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT, - DCACHE_WRITETHROUGH); - } - - /* - * The default implementation of this function allows the DRAM dcache - * to be enabled only after relocation. However, to speed up ECC - * initialization, we want to be able to enable DRAM dcache before - * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram - * is set first). - */ - start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; - for (i = start; i < start + size; i++) - set_section_dcache(i, DCACHE_DEFAULT_OPTION); -}
Reviewed-by: Tien Fong Chee <[email protected]> Best regards, Tien Fong
