Hi,
> In the current implementation, the dummy buswidth is set equal to the
> address buswidth. In case of quad SPI (mode 1-1-4), where the address
> width is 1, the dummy buswidth is also set to 1. Due to this, the
> controller driver introduces 8 dummy cycles on the data line (D0) only
> during a read operation.
Doesn't the controller driver introduce 8 dummy 'clock' cycles that
makes all data lines (D3..D0) idle (typically High-Z) before reading?
>
> Since 4 data lines are used in quad SPI mode, the dummy buswidth should
> be set to 4. The controller driver computes the number of dummy clock
> cycles as:
>
> dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
>
> With dummy.buswidth corrected to 4, the controller produces 2 clock
> cycles of dummy spread across all 4 data lines (D0-D3), which is
> equivalent to 8 dummy bit-times, the same as before. This fix applies
> to all bus width configurations (single, dual, quad and octal).
MTD driver converts dummy cycles to dummy bytes by:
op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8;
So, if you change the dummy.buswidth, the controller driver will get
same number of dummy_cycles.
>
> Signed-off-by: Padmarao Begari <[email protected]>
> ---
> drivers/mtd/spi/spi-nor-core.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
> index 937d79af64e..19446265cd5 100644
> --- a/drivers/mtd/spi/spi-nor-core.c
> +++ b/drivers/mtd/spi/spi-nor-core.c
> @@ -264,7 +264,7 @@ void spi_nor_setup_op(const struct spi_nor *nor,
> op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);
>
> if (op->dummy.nbytes)
> - op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);
> + op->dummy.buswidth = spi_nor_get_protocol_data_nbits(proto);
>
> if (op->data.nbytes)
> op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
> --
> 2.34.1
Thanks,
Takahiro
