Hi Andreas,
On 6/20/26 12:08 AM, Andreas Zdziarstek wrote:
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Default is a second global reset which causes a system hang on a timeout
in U-Boot.
Verified on the Hardkernel ODROID-M1S (RK3566): a watchdog timeout now
cleanly reboots the board.
Signed-off-by: Andreas Zdziarstek <[email protected]>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c
b/arch/arm/mach-rockchip/rk3568/rk3568.c
index 2b1eafee37c..77610a6a6ec 100644
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -37,6 +37,10 @@
#define CPU_GRF_BASE 0xfdc30000
#define GRF_CORE_PVTPLL_CON0 (0x10)
+#define CRU_BASE 0xfdd20000
+#define CRU_GLB_RST_CON (CRU_BASE + 0x0dc)
+#define WDT_GLB_SRST_CTRL BIT(1)
+
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
@@ -146,6 +150,10 @@ int arch_cpu_init(void)
writel((PMU_PD_VO_DWN_ENA << 16),
PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
#endif
+
+ /* Make WDT trigger a first global reset */
+ setbits_le32((void __iomem *)CRU_GLB_RST_CON, WDT_GLB_SRST_CTRL);
+
You should be able to use:
#define CRU_BASE 0xfdd20000
int arch_cpu_init(void)
{
static struct rk3568_cru * const cru = (void *)CRU_BASE;
[...]
setbits_le32(&cru->glb_rst_con, WDT_GLB_SRST_CTRL);
}
and it would match how we did it for PX30. It's not a big deal if we
keep's in this patch though.
I think we should probably enable the second global reset for TSADC as
well, like we did on PX30. While we don't have a driver for it in
U-Boot, we do in the Linux kernel and we don't configure the global
reset level there I think? So a thermal shutdown would properly also
reset the whole SoC (or as much as allowed by Rockchip :) ).
What do you think?
Cheers,
Quentin
