[PATCH 2/2] arm: mach-omap2: am33xx: check VTP before reinitalizing

[Bryan Brattlof]

During a warm reset, the DDR controller will be put into a self refresh
state and will exit self refresh on reset release which will put the
controller in a ready state during bootup.

However we will reinitialize the controller regardless which will
temporarily (~6us) glitch the DDR_RESET line low

Fix this by checking if the VTP controller is already in a ready state
before we initialize the controller unnecessarily.

Fixes: 3ba65f97cbed ("am33xx: refactor emif4/ddr to support multiple EMIF 
instances")
Signed-off-by: Bryan Brattlof <b...@ti.com>
---
 arch/arm/mach-omap2/am33xx/emif4.c | 21 +++++++++++++++------
 1 file changed, 15 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/am33xx/emif4.c 
b/arch/arm/mach-omap2/am33xx/emif4.c
index f19c66822d20..96e239b31a0f 100644
--- a/arch/arm/mach-omap2/am33xx/emif4.c
+++ b/arch/arm/mach-omap2/am33xx/emif4.c
@@ -29,12 +29,21 @@ static struct cm_device_inst *cm_device =
 
 static void config_vtp(int nr)
 {
-       writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
-                       &vtpreg[nr]->vtp0ctrlreg);
-       writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
-                       &vtpreg[nr]->vtp0ctrlreg);
-       writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
-                       &vtpreg[nr]->vtp0ctrlreg);
+       /*
+        * A warm reset will result in DDR going into self refresh. Once the
+        * reset is released we will exit self refresh and resume normally
+        * so a reinitialization of the controller is not needed.
+        *
+        * Check to see if VTP is ready before we reinitialize the controller
+        */
+       if ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != 
VTP_CTRL_READY) {
+               writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+                      &vtpreg[nr]->vtp0ctrlreg);
+               writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+                      &vtpreg[nr]->vtp0ctrlreg);
+               writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+                      &vtpreg[nr]->vtp0ctrlreg);
+       }
 
        /* Poll for READY */
        while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=

-- 
2.54.0