From: "Thomas Richard (TI)" <[email protected]> Add support for resuming from suspend in board_init_f. The resume state of the SOC is identified and lpm resume sequence is followed accordingly.
First, add the board specific part of the exit retention sequence for k3-ddrss following the DDR resume sequence: - exit DDR from retention - de-assert the DDR_RET pin - restore DDR max frequency - exit DDR from low power Then: - Extract context address from devicetree and send to TIFS. - Power on the rproc cluster. - Replay the certificates attached to saved images of ATF and OPTEE. - Resume sequence for context restore and rproc resume. - Image entry to DM firmware. (All those steps are done in do_resume()) The context address area is firewalled by TIFS to protect it from other hosts. Co-developed-by: Gregory CLEMENT (TI) <[email protected]> Signed-off-by: Gregory CLEMENT (TI) <[email protected]> Signed-off-by: Thomas Richard (TI) <[email protected]> Co-developed-by: Prasanth Babu Mantena <[email protected]> Signed-off-by: Prasanth Babu Mantena <[email protected]> Co-developed-by: Richard Genoud (TI) <[email protected]> Signed-off-by: Richard Genoud (TI) <[email protected]> --- arch/arm/mach-k3/j721e/j721e_init.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/mach-k3/j721e/j721e_init.c b/arch/arm/mach-k3/j721e/j721e_init.c index f9af0288cf66..fce6702be687 100644 --- a/arch/arm/mach-k3/j721e/j721e_init.c +++ b/arch/arm/mach-k3/j721e/j721e_init.c @@ -20,9 +20,12 @@ #include <mmc.h> #include <remoteproc.h> #include <k3-avs.h> +#include <power/pmic.h> +#include <mach/k3-ddr.h> #include "../sysfw-loader.h" #include "../common.h" +#include "../lpm-common.h" /* NAVSS North Bridge (NB) registers */ #define NAVSS0_NBSS_NB0_CFG_MMRS 0x03802000 @@ -46,6 +49,10 @@ #define DEV_A72SS0_CORE0_ID 4 #define DEV_A72SS0_CORE0_MSMC_CLK_ID 1 +/* DDR retention bits */ +#define DDR_RET_VAL BIT(1) +#define DDR_RET_CLK BIT(2) + #ifdef CONFIG_K3_LOAD_SYSFW struct fwl_data cbass_hc_cfg0_fwls[] = { #if defined(CONFIG_SOC_K3_J721E) @@ -298,6 +305,7 @@ void board_init_f(ulong dummy) { int ret; #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW) + struct k3_ddrss_regs regs; struct udevice *dev; #endif /* @@ -410,6 +418,22 @@ void board_init_f(ulong dummy) ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) panic("DRAM init failed: %d\n", ret); + + if (j7xx_board_is_resuming()) { + /* + * The DDR resume sequence is: + * - exit DDR from retention + * - de-assert the DDR_RET pin + * - restore DDR max frequency + * - exit DDR from low power + */ + k3_ddrss_lpddr4_exit_retention(dev, ®s); + k3_deassert_ddr_ret("pmic@4c", DDR_RET_VAL, DDR_RET_CLK, true); + k3_ddrss_lpddr4_change_freq(dev); + k3_ddrss_lpddr4_exit_low_power(dev, ®s); + + do_resume(); + } #endif spl_enable_cache();
