This series makes the Synopsys DesignWare watchdog usable on rk3566/rk3568 and enables it on the Hardkernel ODROID-M1S.
On current next the dw-wdt driver already probes (d62801d09441), but a timeout or "wdt expire" still hangs the SoC: CRU_GLB_RST_CON routes the watchdog to the second global reset by default, which causes a hung SoC. Patch 1 routes the watchdog to the first global reset instead, same as the PX30 implementation. Patch 2 does the same for the TSADC, so a thermal shutdown also resets the whole SoC. Patch 3 enables the watchdog (wdt command only, no autostart to be non-breaking) on the ODROID-M1S. Verified on the ODROID-M1S (RK3566): a watchdog timeout cleanly reboots the board. Changes in v3: - patch 1: keep the glb_rst_con write inside CONFIG_XPL_BUILD (review comment by Jonas) - patch 2: fold the WDT and TSADC bits into a single glb_rst_con read-modify-write instead of two separate ones (review comment by Jonas) Changes in v2: - patch 1: access CRU_GLB_RST_CON through the rk3568_cru struct, matching PX30's arch_cpu_init() (review comment by Quentin) - patch 2 (new): also route the TSADC to a first global reset (review comment by Quentin) - patch 3 (was 2/2): unchanged On the TSADC (patch 2): while checking how the ODROID-M1S comes up, I noticed the rkbin DDR init (probably, at least I don't know what else could set it at that stage) already sets the TSADC bit in CRU_GLB_RST_CON before U-Boot runs. So, on this board the patch is effectively a no-op. It still seems right to configure it explicitly in U-Boot rather than depend on the firmware blob, and it matches what PX30 does. Andreas Zdziarstek (3): rockchip: rk3568: make the WDT trigger a first global reset rockchip: rk3568: make the TSADC trigger a first global reset rockchip: odroid-m1s: enable watchdog support arch/arm/mach-rockchip/rk3568/rk3568.c | 11 +++++++++++ configs/odroid-m1s-rk3566_defconfig | 5 +++++ 2 files changed, 16 insertions(+) base-commit: 835a18f80f25731dc818bf9b771bfa111ea3dbeb -- 2.53.0
