From: Marek Vasut <[email protected]> Sent: Thursday, June 25, 2026 4:17 PM > The current DRAM calibration sequence is implemented based on NXP > AN4467 Rev.2 03/2015, which in chapter "12.3.2 Calibration Sequence > Setup with Predefined Data Content" states: > > " > 9. For each of the DQSx: > - Read the HW_DG_UPx value from the MMDC0/1_MPDGHWSTx, subtract the > value of 0xc0 (3/4 cycle). > " > > However, the i.MX 6Solo/6DualLite Applications Processor Reference > Manual, Rev. 5, 05/2020, chapter "45.11.3.1.2 Hardware DQS Calibration > with pre-defined value" states: > > " > 35. Set (MPDGHWSTn[HW_DG_UPn][10:7] - 1) to MPDGCTRLn[DG_HC_DELn]. > (We set the DQS gating value to be the upper limit value minus > 1 half cycle) > " > > The i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 6, > 05/2020, chapter 44.11.3.1.2 Hardware DQS Calibration with pre-defined > value lists the same information. So do the following manuals: > > - i.MX 6DualPlus/6QuadPlus Applications Processor Reference Manual, Rev. 3, > 05/2020 > chapter 46.11.3.1.2 Hardware DQS Calibration with pre-defined value > - i.MX 6SoloX Applications Processor Reference Manual, Rev. 4, 05/2020 > chapter 40.11.3.1.2 Hardware DQS Calibration with pre-defined value > - i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017 > chapter 33.11.3.1.2 Hardware DQS Calibration with pre-defined value > - i.MX 6ULL Applications Processor Reference Manual, Rev. 1, 11/2017 > chapter 35.11.3.1.2 Hardware DQS Calibration with pre-defined value > - i.MX 6ULZ Applications Processor Reference Manual, Rev. 0, 10/2018 > chapter 29.11.3.1.2 Hardware DQS Calibration with pre-defined value > > The NXP MMDC DDR Stress Test (3.0.0) tool seems to be have the same > way as the later document rather than the AN4467 application note, > and produces values similar to the values with subtracted 1/2 cycle. > > Adjust the behavior to match the more recent Reference Manual and > the MMDC calibration tool. > > Winbond W634GU6RB does show sporadic signs of instability without > this correction. > > Signed-off-by: Marek Vasut <[email protected]> > --- > Cc: "NXP i.MX U-Boot Team" <[email protected]> > Cc: Adam Ford <[email protected]> > Cc: Alice Guo <[email protected]> > Cc: Fabio Estevam <[email protected]> > Cc: Francesco Dolcini <[email protected]> > Cc: Frieder Schrempf <[email protected]> > Cc: Heiko Schocher <[email protected]> > Cc: Markus Niebel <[email protected]> > Cc: Michael Walle <[email protected]> > Cc: Peng Fan <[email protected]> > Cc: Stefano Babic <[email protected]> > Cc: Tim Harvey <[email protected]> > Cc: Tom Rini <[email protected]> > Cc: [email protected] > Cc: [email protected] > --- > arch/arm/mach-imx/mx6/ddr.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c > index 5a1258e002d..2447698cfe4 100644 > --- a/arch/arm/mach-imx/mx6/ddr.c > +++ b/arch/arm/mach-imx/mx6/ddr.c > @@ -71,13 +71,13 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, > u32 > *reg_ctrl) > val_ctrl = readl(reg_ctrl); > val_ctrl &= 0xf0000000; > > - dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0xc0; > + dg_tmp_val = ((readl(reg_st0) & 0x07ff0000) >> 16) - 0x80; > dg_dl_abs_offset = dg_tmp_val & 0x7f; > dg_hc_del = (dg_tmp_val & 0x780) << 1; > > val_ctrl |= dg_dl_abs_offset + dg_hc_del; > > - dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0xc0; > + dg_tmp_val = ((readl(reg_st1) & 0x07ff0000) >> 16) - 0x80; > dg_dl_abs_offset = dg_tmp_val & 0x7f; > dg_hc_del = (dg_tmp_val & 0x780) << 1;
We tested it with a DH electronics i.MX6Solo SoM in the climate chamber. With Winbond W634GU6RB and this patch instability issues with some SoMs were gone. In addition, we tested the following memory types (also with a DH electronics i.MX6Solo SoM) in the climate chamber with this patch to rule out any fundamental issues with it: - Intelligent Memory IM4G16D3FABG-125I - Samsung K4B4G1646E-BMMA - Etron EM6HE16EWAKG-10IH Tested-by: Christoph Niedermaier <[email protected]> Regards Christoph
