On Thu, Jul 02, 2026 at 11:25:39AM +0100, Simon Glass wrote: > Hi Yao, > > On 2026-07-01T11:17:53, Yao Zi <[email protected]> wrote: > > LoongArch: CPU assembly routines > > > > start.S for initialisation, smp_secondary routine for > > a spin-table like interface for secondary cpus. > > > > Signed-off-by: Jiaxun Yang <[email protected]> > > Signed-off-by: Yao Zi <[email protected]> > > > > arch/loongarch/cpu/Makefile | 4 + > > arch/loongarch/cpu/cpu.c | 27 ++++++ > > arch/loongarch/cpu/smp_secondary.S | 55 ++++++++++++ > > arch/loongarch/cpu/start.S | 170 > > +++++++++++++++++++++++++++++++++++++ > > 4 files changed, 256 insertions(+)
... > > diff --git a/arch/loongarch/cpu/smp_secondary.S > > b/arch/loongarch/cpu/smp_secondary.S > > @@ -0,0 +1,55 @@ > > +1: > > + /* Query spin table */ > > + idle 0 > > + nop > > + iocsrrd.w t0, t1 > > + beqz t0, 1b > > Is the nop after idle 0 required by the ISA (to guarantee the > wake-up completes before the load) or just padding? A > one-line comment would help. I don't think such requirements exist, and LoongArch instructions are always 4-byte so there's nothing to pad, too. This is likely unintentionally left when re-writing the assembly, and I'll remove it in the next version. > Regards, > Simon Best regards, Yao Zi
