The GIC redistributor base address depends on the part: the 2VM3654 device has 4 APU cores and 3 GIC ITS blocks, which shifts the redistributor region up compared to the base 8 core / single ITS part. A single U-Boot binary must therefore pick the right base at runtime instead of relying on the compile-time GICR_BASE used by the generic lowlevel_init().
Add a SoC specific lowlevel_init() that reads the PMC TAP IDCODE and selects GICR_BASE_2VM3654 for the 2VM3654 device, otherwise keeps the default GICR_BASE. CONFIG_ARMV8_MULTIENTRY is not supported on Versal Gen 2 so the generic slave handling is intentionally dropped. Signed-off-by: Michal Simek <[email protected]> --- Changes in v2: - Also make hardware.h assembly safe arch/arm/mach-versal2/Makefile | 1 + arch/arm/mach-versal2/lowlevel_init.S | 40 +++++++++++++++++++++++++++ include/configs/amd_versal2.h | 9 ++++++ 3 files changed, 50 insertions(+) create mode 100644 arch/arm/mach-versal2/lowlevel_init.S diff --git a/arch/arm/mach-versal2/Makefile b/arch/arm/mach-versal2/Makefile index 96497b1dfd0a..73b3c8a6f357 100644 --- a/arch/arm/mach-versal2/Makefile +++ b/arch/arm/mach-versal2/Makefile @@ -8,3 +8,4 @@ obj-y += clk.o obj-y += cpu.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-versal2/lowlevel_init.S b/arch/arm/mach-versal2/lowlevel_init.S new file mode 100644 index 000000000000..8bfe50b806e3 --- /dev/null +++ b/arch/arm/mach-versal2/lowlevel_init.S @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SoC specific lowlevel_init for AMD Versal Gen 2 + * + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include <asm-offsets.h> +#include <config.h> +#include <linux/linkage.h> +#include <asm/macro.h> +#include <asm/arch/hardware.h> + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + +#if defined(CONFIG_GICV3) + branch_if_slave x0, 1f + ldr x0, =GICD_BASE + bl gic_init_secure +1: + /* + * Pick the redistributor base for this part. Default to GICR_BASE + * and switch to GICR_BASE_2VM3654 when the PMC TAP IDCODE matches + * the 2VM3654 device. + */ + ldr x0, =GICR_BASE + ldr x1, =PMC_TAP_IDCODE + ldr w1, [x1] + ldr w2, =GICR_IDCODE_2VM3654 + cmp w1, w2 + b.ne 3f + ldr x0, =GICR_BASE_2VM3654 +3: + bl gic_init_secure_percpu +#endif + + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index a07e12bd1468..00627dcd9433 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -19,6 +19,15 @@ #define GICD_BASE 0xe2000000 #define GICR_BASE 0xe2060000 +/* + * The 2VM3654 part has 4 APU cores and 3 GIC ITS blocks (vs 8 cores and a + * single ITS on the base part), which moves the redistributor region up by + * the two extra ITS blocks. The right base is selected at runtime in + * lowlevel_init() based on the PMC TAP IDCODE. + */ +#define GICR_BASE_2VM3654 0xe20a0000 +#define GICR_IDCODE_2VM3654 0x04d98093 + /* Serial setup */ #define CFG_SYS_BAUDRATE_TABLE \ { 4800, 9600, 19200, 38400, 57600, 115200 } --- base-commit: 3278a671cb521d898e6f49d35f6bc034b2ac4d46 branch: debian-sent3 -- 2.43.0
