On lemans/sa8775p, the SDCC1 apps clock high-speed rates (192 and 384 MHz) source from GPLL9 (ftbl_gcc_sdcc1_apps_clk_src), but the driver never enables GPLL9. When SDCC1 is set to such a rate the RCG switches its source to a PLL that is off, so the CMD_RCGR update bit never self-clears and U-Boot warns:
WARNING: RCG @ 0x120014 stuck at off Vote GPLL9 on before selecting it as the SDCC1 source, mirroring how clock-sm8250.c enables GPLL9 for SDCC2. GPLL9's mode/status register is at 0x9000 (lock is bit 31) and its enable vote is bit 9 of the APCS GPLL vote register 0x4b028, matching gcc-sa8775p.c in Linux. Not hardware-validated for SDCC high speed: the board this was found on (Qualcomm IQ-9075 / Lemans EVK) boots from UFS with no SD card populated, so here it only clears the stuck-RCG warning. Build-tested on lemans. Signed-off-by: Royyan Zahir <[email protected]> --- drivers/clk/qcom/clock-sa8775p.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -26,6 +26,9 @@ #define SDCC1_APPS_CLK_CMD_RCGR 0x20014 +#define APCS_GPLL9_STATUS 0x9000 +#define APCS_GPLLX_ENA_REG 0x4b028 + #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) @@ -90,6 +93,14 @@ { } }; +/* GPLL9 (SDCC1 high-speed source) is not enabled by earlier boot stages. */ +static const struct pll_vote_clk gpll9_vote_clk = { + .status = APCS_GPLL9_STATUS, + .status_bit = BIT(31), + .ena_vote = APCS_GPLLX_ENA_REG, + .vote_bit = BIT(9), +}; + static ulong sa8775p_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -130,6 +141,9 @@ return 19200000; case GCC_SDCC1_APPS_CLK: freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate); + /* SDCC1 high-speed rates source from GPLL9; vote it on first. */ + if (freq->src == CFG_CLK_SRC_GPLL9) + clk_enable_gpll0(priv->base, &gpll9_vote_clk); clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR, freq->pre_div, freq->m, freq->n, freq->src, 8); return freq->freq;
