Hi Tien Fong, > Instance decodes 0x100; reserved offsets are RAZ/WI” (or equivalent wording). > If TRM does not guarantee benign behavior for reserved offsets, I’d NAK 0x100 > and request to keep 0x4 until there’s a concrete need to program additional > offsets. Please check if only 0xFFD21400 is valid and accessing other offsets > may bus fault / return unpredictable / hit other logic? >
The 0x100 comes directly from the documentation here: https://www.intel.com/content/www/us/en/programmable/hps/ stratix-10/index.html#miv1505407144600.html 0xFFD21400–0xFFD214FF (256 B) owned entirely by this one firewall instance (next block is at 0xFFD22000), so reg size 0x100 matches the hardware decode window. On the safety concern: the intel,socfpga-dtreg driver never accesses reserved offsets. reg[1] is used only as a bounds check (blk_sz < offset + 4); the driver only reads/writes offsets listed in intel,offset-settings here just offset 0x0. So 0x4 vs 0x100 makes no behavioral difference for this node; nothing in 0x004–0x0FF is ever touched. Regards, Boon Khai
