Hello.
On 05-08-2011 18:44, Kumar Gala wrote:
> From: Poonam Aggrwal<poonam.aggr...@freescale.com>
> For an IFC Erratum (A-003399) we will need to access IFC registers in
> cpu_init_early_f() so expand the TLB covering CCSR to 1M.
> Since we need a TLB to cover 1M we move to using TLB1 array for all the
> early mappings so we can cover various sizes beyond 4k.
> Additionally removed volatile from ccsr_virt declaration as its not needed
> for IO accessors
I don't see that change in the patch...
> Signed-off-by: Poonam Aggrwal<poonam.aggr...@freescale.com>
> Signed-off-by: Kumar Gala<ga...@kernel.crashing.org>
> ---
> arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 7 ++++---
> 1 files changed, 4 insertions(+), 3 deletions(-)
> diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
> b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
> index 64eda94..359f03e 100644
> --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
> +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
> @@ -21,6 +21,7 @@
> #include <asm/processor.h>
> #include <asm/mmu.h>
> #include <asm/fsl_law.h>
> +#include <asm/io.h>
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -40,8 +41,8 @@ void cpu_init_early_f(void)
> for (i = 0; i< sizeof(gd_t); i++)
> ((char *)gd)[i] = 0;
>
> - mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(0);
> - mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_4K);
> + mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
> + mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
> mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
> mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
> mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
> @@ -49,6 +50,6 @@ void cpu_init_early_f(void)
> write_tlb(mas0, mas1, mas2, mas3, mas7);
>
> init_laws();
> - invalidate_tlb(0);
> + invalidate_tlb(1);
> init_tlbs();
> }
WBR, Sergei
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