Signed-off-by: Anton Staaf <robot...@chromium.org>
Cc: Mike Frysinger <vap...@gentoo.org>
Cc: Lukasz Majewski <l.majew...@samsung.com>
Cc: Jason Jin <jason....@freescale.com>
---
 arch/m68k/include/asm/cache.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index 7c84e48..5c9bb30 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -207,4 +207,14 @@ void dcache_invalid(void);
 
 #endif
 
+/*
+ * m68k uses 16 byte L1 data cache line sizes.  Use this for DMA buffer
+ * alignment unless the board configuration has specified a new value.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN      16
+#endif
+
 #endif                         /* __CACHE_H */
-- 
1.7.3.1

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