On 10/26/2011 11:13 PM, Tom Rini wrote: > This introduces 200MHz Micron parts timing information based on x-loader > and re-organizes the file slightly for grouping. The memory init logic > is also based on what x-loader does in these cases. Note that while > previously u-boot would be flashed in with SW ECC in this case it now > must be flashed with HW ECC.
You have two spaces between the sentences, why is that? > Beagleboard rev C5, xM rev A: > Tested-by: Tom Rini <[email protected]> > Beagleboard xM rev C: > Tested-by: Matt Ranostay <[email protected]> > Beagleboard rev B7, C2, xM rev B: > Tested-by: Matt Porter <[email protected]> > Signed-off-by: Tom Rini <[email protected]> > --- > arch/arm/include/asm/arch-omap3/mem.h | 24 +++++ > board/ti/beagle/beagle.c | 160 > ++++++++++++++++++++++++++++++++- > board/ti/beagle/config.mk | 33 ------- > include/configs/omap3_beagle.h | 60 ++++++++++++- > 4 files changed, 242 insertions(+), 35 deletions(-) > delete mode 100644 board/ti/beagle/config.mk config.mk removal does not belong to that patch... It should be a separate one, say cleanup patch. > diff --git a/arch/arm/include/asm/arch-omap3/mem.h > b/arch/arm/include/asm/arch-omap3/mem.h > index af3504c..a784813 100644 > --- a/arch/arm/include/asm/arch-omap3/mem.h > +++ b/arch/arm/include/asm/arch-omap3/mem.h > @@ -171,6 +171,30 @@ enum { > #define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ > (MICRON_SIL << 3) | (MICRON_BL)) > > + > +/* Micron part (200MHz optimized) 5 ns > + */ > +#define MICRON_TDAL_200 6 > +#define MICRON_TDPL_200 3 > +#define MICRON_TRRD_200 2 > +#define MICRON_TRCD_200 3 > +#define MICRON_TRP_200 3 > +#define MICRON_TRAS_200 8 > +#define MICRON_TRC_200 11 > +#define MICRON_TRFC_200 15 > +#define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | (MICRON_TRC_200 << > 22) | (MICRON_TRAS_200 << 18) \ > + | (MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) > |(MICRON_TRRD_200 << 9) | \ > + (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200)) MICRON_TDAL_200 does not need parenthesis. > + > +#define MICRON_TWTR_200 2 > +#define MICRON_TCKE_200 4 > +#define MICRON_TXP_200 2 > +#define MICRON_XSR_200 23 > +#define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << > 0)) | \ > + (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16) > +#define MICRON_ARCV_200 0x5e6 > +#define MICRON_V_RFR_CTRL_200 ((MICRON_ARCV_200 << 8) | (MICRON_ARE)) same here with MICRON_ARE > + > /* > * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns > * ACTIMA > diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c > index aa5047c..a77b0cb 100644 > --- a/board/ti/beagle/beagle.c > +++ b/board/ti/beagle/beagle.c > @@ -34,9 +34,11 @@ > #include <status_led.h> > #endif > #include <twl4030.h> > +#include <linux/mtd/nand.h> > #include <asm/io.h> > #include <asm/arch/mmc_host_def.h> > #include <asm/arch/mux.h> > +#include <asm/arch/mem.h> > #include <asm/arch/sys_proto.h> > #include <asm/gpio.h> > #include <asm/mach-types.h> > @@ -139,6 +141,160 @@ int get_board_revision(void) > return revision; > } > > +#ifdef CONFIG_SPL_BUILD > + > +#define MICRON_DDR 0 > +#define NUMONYX_MCP 1 > +#define MICRON_MCP 2 > + > +#define NAND_CMD_STATUS 0x70 > +#define NAND_CMD_READID 0x90 > +#define NAND_CMD_RESET 0xff > + > +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C) > +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80) > +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84) Why not use tabs for alignment? > + > +#define WRITE_NAND_COMMAND(d, adr) \ > + do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d;} while(0) > +#define WRITE_NAND_ADDRESS(d, adr) \ > + do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d;} while(0) > +#define READ_NAND(adr) (*(volatile u16 *)GPMC_NAND_DATA_0) This is definitely needs a cleanup... Consider Sanjeev's proposal. If it will not work for some reason, you need at least to use writel() readl() io accessors. > + > +/* nand_command: Send a flash command to the flash chip */ > +static void nand_command(unsigned char command) > +{ > + WRITE_NAND_COMMAND(command, NAND_ADDR); > + > + if (command == NAND_CMD_RESET) { > + unsigned char ret_val; > + nand_command(NAND_CMD_STATUS); > + do { > + ret_val = READ_NAND(NAND_ADDR);/* wait till ready */ > + } while ((ret_val & 0x40) != 0x40); You should be using some kind of timeout, so you will not stuck in here without being noticed. > + } > +} > + > +/* > + * In order to find out what DDR we have we need to see what NAND we > + * may have. This relies on having already initalized GPMC earlier Two spaces? > + * in the sequence. > + */ > +static void nand_readid(int *mfr, int *id) > +{ > + nand_command(NAND_CMD_RESET); > + nand_command(NAND_CMD_READID); > + > + WRITE_NAND_ADDRESS(0x0, NAND_ADDR); > + > + /* Read off the manufacturer and device id. */ > + *mfr = READ_NAND(NAND_ADDR); > + *id = READ_NAND(NAND_ADDR); > +} > + > +#define GPMC_CONFIG_CS0_CONFIG1 0x6E000060 > +#define GPMC_CONFIG_CS0_CONFIG2 0x6E000064 > +#define GPMC_CONFIG_CS0_CONFIG3 0x6E000068 > +#define GPMC_CONFIG_CS0_CONFIG4 0x6E00006C > +#define GPMC_CONFIG_CS0_CONFIG5 0x6E000070 > +#define GPMC_CONFIG_CS0_CONFIG6 0x6E000074 > +#define GPMC_CONFIG_CS0_CONFIG7 0x6E000078 > +#define OMAP34XX_GPMC_CS0_SIZE 0x8 Why do you need two tabs in all the above defines? And yes, Sanjeev is right. > + > +static int identify_xm_ddr(void) > +{ > + int mfr, id; > + > + /* Make sure that we have setup GPMC for NAND correctly. */ > + writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG_CS0_CONFIG1); > + writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG_CS0_CONFIG2); > + writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG_CS0_CONFIG3); > + writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG_CS0_CONFIG4); > + writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG_CS0_CONFIG5); > + writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG_CS0_CONFIG6); > + > + /* Enable the GPMC Mapping */ > + writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF) << 8) | > + ((NAND_BASE >> 24) & 0x3F) | > + (1 << 6)), (GPMC_CONFIG_CS0_CONFIG7)); White space problems, unneeded parenthesis. > + > + sdelay(2000); > + > + nand_readid(&mfr, &id); > + if (mfr == 0) > + return MICRON_DDR; > + if ((mfr == 0x20) && (id == 0xba)) parenthesis > + return NUMONYX_MCP; > + if ((mfr == 0x2c) && (id == 0xbc)) parenthesis > + return MICRON_MCP; > + > + /* Unknown. */ > + return -1; > +} > + > +/* > + * Routine: board_early_sdrc_init wrong > + * Description: If we use SPL then there is no x-loader nor config header > + * so we have to setup the DDR timings outself on both banks. > + */ > +void get_board_mem_timings(u32 *cs_cfg, u32 *mcfg, u32 *ctrla, u32 *ctrlb, > + u32 *rfr_ctrl, u32 *mr) > +{ > + /* TODO XXX REWORD */ > + /* We have magic hard coded values here for V_MCFG which come from > + * x-loader as they do not match how the OMAP35x TRM says to > + * calculate them values. */ multi line comment should be: /* * blabla */ > + *mr = MICRON_V_MR; > + switch (get_board_revision()) { > + case REVISION_C4: > + if (identify_xm_ddr() == NUMONYX_MCP) { > + *cs_cfg = 0x4; > + *mcfg = 0x04590099; > + *ctrla = NUMONYX_V_ACTIMA_165; > + *ctrlb = NUMONYX_V_ACTIMB_165; > + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; aligning the assignments above (and below) will make it much more readable > + } else if (identify_xm_ddr() == MICRON_MCP) { > + /* Beagleboard Rev C5 */ > + *cs_cfg = 0x2; > + *mcfg = 0x03588099; > + *ctrla = MICRON_V_ACTIMA_200; > + *ctrlb = MICRON_V_ACTIMB_200; > + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; > + } else { > + *cs_cfg = 0x1; > + *mcfg = 0x02584099; > + *ctrla = MICRON_V_ACTIMA_165; > + *ctrlb = MICRON_V_ACTIMB_165; > + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; > + } > + break; > + case REVISION_XM_A: > + case REVISION_XM_B: > + case REVISION_XM_C: > + if (identify_xm_ddr() == MICRON_DDR) { > + *cs_cfg = 0x2; > + *mcfg = 0x03588099; > + *ctrla = MICRON_V_ACTIMA_200; > + *ctrlb = MICRON_V_ACTIMB_200; > + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; > + } else { > + *cs_cfg = 0x4; > + *mcfg = 0x04590099; > + *ctrla = NUMONYX_V_ACTIMA_165; > + *ctrlb = NUMONYX_V_ACTIMB_165; > + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; > + } > + break; > + default: > + *cs_cfg = 0x1; > + *mcfg = 0x02584099; > + *ctrla = MICRON_V_ACTIMA_165; > + *ctrlb = MICRON_V_ACTIMB_165; > + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; > + } > +} > +#endif > + > /* > * Routine: get_expansion_id > * Description: This function checks for expansion board by checking I2C > @@ -371,7 +527,7 @@ void set_muxconf_regs(void) > MUX_BEAGLE(); > } > > -#ifdef CONFIG_GENERIC_MMC > +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) This should be another patch. > int board_mmc_init(bd_t *bis) > { > omap_mmc_init(0); > @@ -480,6 +636,7 @@ int ehci_hcd_init(void) > > #endif /* CONFIG_USB_EHCI */ > > +#ifndef CONFIG_SPL_BUILD > /* > * This command returns the status of the user button on beagle xM > * Input - none > @@ -534,3 +691,4 @@ U_BOOT_CMD( > "Return the status of the BeagleBoard USER button", > "" > ); > +#endif > diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk > deleted file mode 100644 > index cf055db..0000000 > --- a/board/ti/beagle/config.mk > +++ /dev/null > @@ -1,33 +0,0 @@ > -# > -# (C) Copyright 2006 > -# Texas Instruments, <www.ti.com> > -# > -# Beagle Board uses OMAP3 (ARM-CortexA8) cpu > -# see http://www.ti.com/ for more information on Texas Instruments > -# > -# See file CREDITS for list of people who contributed to this > -# project. > -# > -# This program is free software; you can redistribute it and/or > -# modify it under the terms of the GNU General Public License as > -# published by the Free Software Foundation; either version 2 of > -# the License, or (at your option) any later version. > -# > -# This program is distributed in the hope that it will be useful, > -# but WITHOUT ANY WARRANTY; without even the implied warranty of > -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > -# GNU General Public License for more details. > -# > -# You should have received a copy of the GNU General Public License > -# along with this program; if not, write to the Free Software > -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > -# MA 02111-1307 USA > -# > -# Physical Address: > -# 8000'0000 (bank0) > -# A000/0000 (bank1) > -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 > -# (mem base + reserved) > - > -# For use with external or internal boots. > -CONFIG_SYS_TEXT_BASE = 0x80008000 > diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h > index a026478..a126566 100644 > --- a/include/configs/omap3_beagle.h > +++ b/include/configs/omap3_beagle.h > @@ -347,7 +347,7 @@ > */ > #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ > #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 > -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ > +#define PHYS_SDRAM_1_SIZE (32 << 20) /* At least 32 MiB */ > #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 > > /* SDRAM Bank Allocation method */ > @@ -390,4 +390,62 @@ > > #define CONFIG_OMAP3_SPI > > +/* Defines for SPL */ > +#define CONFIG_SPL > +#define CONFIG_SPL_NAND_SIMPLE > +#define CONFIG_SPL_TEXT_BASE 0x40200800 > +#define CONFIG_SPL_MAX_SIZE (45 * 1024) > +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK > + > +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 > +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ alignment > + > +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address > 0x60000 */ > +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ > +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 > +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" ditto > + > +#define CONFIG_SPL_LIBCOMMON_SUPPORT > +#define CONFIG_SPL_LIBDISK_SUPPORT > +#define CONFIG_SPL_I2C_SUPPORT > +#define CONFIG_SPL_LIBGENERIC_SUPPORT > +#define CONFIG_SPL_MMC_SUPPORT > +#define CONFIG_SPL_FAT_SUPPORT > +#define CONFIG_SPL_SERIAL_SUPPORT > +#define CONFIG_SPL_NAND_SUPPORT > +#define CONFIG_SPL_POWER_SUPPORT > +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" > + > +/* NAND boot config */ > +#define CONFIG_SYS_NAND_5_ADDR_CYCLE > +#define CONFIG_SYS_NAND_PAGE_COUNT 64 > +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 > +#define CONFIG_SYS_NAND_OOBSIZE 64 ditto > +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) > +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 > +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ > + 10, 11, 12, 13} > + > +#define CONFIG_SYS_NAND_ECCSIZE 512 > +#define CONFIG_SYS_NAND_ECCBYTES 3 ditto > + > +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ > + CONFIG_SYS_NAND_ECCSIZE) > +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ > + CONFIG_SYS_NAND_ECCSTEPS) > + > +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE > + > +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 > + > +/* > + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM > + * 64 bytes before this address should be set aside for u-boot.img's > + * header. That is 0x800FFFC0--0x80100000 should not be used for any > + * other needs. > + */ > +#define CONFIG_SYS_TEXT_BASE 0x80100000 > +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 > +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 > + > #endif /* __CONFIG_H */ _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
