Hello Tom,
Tom Rini wrote:
> A number of boards are populated with a PoP chip for both DDR and NAND
> memory. Other boards may simply use this as an easy way to identify
> board revs. So we provide a function that can be called early to reset
> the NAND chip and return the result of NAND_CMD_READID. All of this
> code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
>
> Signed-off-by: Tom Rini <tr...@ti.com>
> ---
> arch/arm/cpu/armv7/omap3/Makefile | 3 +
> arch/arm/cpu/armv7/omap3/spl_id_nand.c | 83
> +++++++++++++++++++++++++++
> arch/arm/include/asm/arch-omap3/sys_proto.h | 1 +
> 3 files changed, 87 insertions(+), 0 deletions(-)
> create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
>
> diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c
> b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
> new file mode 100644
> index 0000000..edf3ded
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c
> @@ -0,0 +1,83 @@
[...]
> +void identify_nand_chip(int *mfr, int *id)
> +{
> + /* Make sure that we have setup GPMC for NAND correctly. */
> + writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
> + writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
> + writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
> + writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
> + writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
> + writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
> +
> + /* Enable the GPMC Mapping */
> + writel((((GPMC_SIZE_128M & 0xF) << 8) | ((NAND_BASE >> 24) & 0x3F) |
^ ^ ^
> + (1 << 6)), &gpmc_config->cs[0].config7);
^^^^^^^^
Please substitute this magic values through defines.
Thanks!
bye,
Heiko
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