On Thu, Nov 10, 2011 at 6:39 PM, Ilya Yanok <ya...@emcraft.com> wrote: > DaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache > enabled by default. So we have to take care and flush/invalidate the > cache before/after the DMA operations. > > Please note that the receive buffer alignment to 32 byte boundary comes > from the old driver version I don't know if it is really needed or > alignment to cache line size is enough. > > Signed-off-by: Ilya Yanok <ya...@emcraft.com>
I don't understand. Didn't you just submit a patch to disable dcache on all boards with EMAC? _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
